{"id":89706,"url":"https://github.com/coderonion/awesome-fpga","name":"awesome-fpga","description":"A collection of some awesome public FPGA projects.","projects_count":274,"last_synced_at":"2026-06-03T16:00:22.008Z","repository":{"id":257811338,"uuid":"825835602","full_name":"coderonion/awesome-fpga","owner":"coderonion","description":"A collection of some awesome public FPGA projects.","archived":false,"fork":false,"pushed_at":"2024-07-08T15:37:17.000Z","size":18,"stargazers_count":4,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2026-05-18T03:03:31.216Z","etag":null,"topics":["awesome","fpga","hdl","risc-v"],"latest_commit_sha":null,"homepage":"","language":null,"has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/coderonion.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2024-07-08T15:36:31.000Z","updated_at":"2025-10-27T15:18:27.000Z","dependencies_parsed_at":"2024-10-05T13:02:19.061Z","dependency_job_id":"4ad3cd35-3a55-40cd-9c83-099a6a1d7a17","html_url":"https://github.com/coderonion/awesome-fpga","commit_stats":null,"previous_names":["coderonion/awesome-fpga"],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/coderonion/awesome-fpga","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/coderonion%2Fawesome-fpga","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/coderonion%2Fawesome-fpga/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/coderonion%2Fawesome-fpga/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/coderonion%2Fawesome-fpga/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/coderonion","download_url":"https://codeload.github.com/coderonion/awesome-fpga/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/coderonion%2Fawesome-fpga/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":33872298,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-05-26T15:22:16.424Z","status":"online","status_checked_at":"2026-06-03T02:00:06.370Z","response_time":59,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"created_at":"2025-06-15T15:16:11.680Z","updated_at":"2026-06-03T16:00:22.008Z","primary_language":null,"list_of_lists":false,"displayable":true,"categories":["Blogs","Applications","Awesome List","Frameworks","Learning Resources"],"sub_categories":[],"readme":"# Awesome-FPGA\r\n[![Awesome](https://cdn.rawgit.com/sindresorhus/awesome/d7305f38d29fed78fa85652e3a63e154dd8e8829/media/badge.svg)](https://github.com/sindresorhus/awesome)\r\n\r\n🔥🔥🔥 This repository lists some awesome public FPGA projects.\r\n\r\n## Contents\r\n- [Awesome-FPGA](#awesome-fpga)\r\n  - [Contents](#contents)\r\n  - [Awesome List](#awesome-list)\r\n  - [Learning Resources](#learning-resources)\r\n  - [Frameworks](#frameworks)\r\n    - [HDL Framework](#hdl-framework)\r\n        - [C HDL](#c-hdl)\r\n        - [Scala HDL](#scala-hdl)\r\n        - [Rust HDL](#rust-hdl)\r\n        - [Python HDL](#python-hdl)\r\n  - [Applications](#applications)\r\n    - [FPGA Applications](#fpga-applications)\r\n    - [Processor Chip](#processor-chip)\r\n        - [CPU Chip](#cpu-chip)\r\n            - [RISC-V Chip](#risc-v-chip)\r\n        - [GPU Chip](#gpu-chip)\r\n    - [IP Module](#ip-module)\r\n        - [IP Generator](#ip-generator)\r\n        - [PCIe Module](#pcie-module)\r\n        - [DDR Module](#ddr-module)\r\n        - [Ethernet Module](#ethernet-module)\r\n        - [WIFI Module](#wifi-module)\r\n        - [UART Module](#uart-module)\r\n        - [USB Module](#usb-module)\r\n        - [CAN-bus Module](#can-bus-module)\r\n        - [AXI Module](#axi-module)\r\n        - [HDMI Module](#hdmi-module)\r\n        - [SD-card Module](#sd-card-module)\r\n        - [NFC Module](#nfc-module)\r\n        - [SATA Module](#sata-module)\r\n        - [DAC Module](#dac-module)\r\n    - [Camera Firmware](#camera-firmware)\r\n    - [Spiking Neural Network](#spiking-neural-network)\r\n    - [Convolutional Neural Network](#convolutional-neural-network)\r\n    - [Object Detection](#object-detection)\r\n    - [Visual SLAM](#visual-slam)\r\n    - [Image Compression](#image-compression)\r\n    - [Motor Control](#motor-control)\r\n    - [Fixed-point](#fixed-point)\r\n  - [Blogs](#blogs)\r\n    - [FPGA Blogs](#fpga-blogs)\r\n\r\n\r\n## Awesome List\r\n\r\n\r\n  - [drom/awesome-hdl](https://github.com/drom/awesome-hdl) \u003cimg src=\"https://img.shields.io/github/stars/drom/awesome-hdl?style=social\"/\u003e : A curated list of amazingly awesome hardware description language projects.\r\n\r\n  - [ben-marshall/awesome-open-hardware-verification](https://github.com/ben-marshall/awesome-open-hardware-verification) \u003cimg src=\"https://img.shields.io/github/stars/ben-marshall/awesome-open-hardware-verification?style=social\"/\u003e : A curated List of Free and Open Source hardware verification tools and frameworks.\r\n\r\n  - [Vitorian/awesome-fpga](https://github.com/Vitorian/awesome-fpga) \u003cimg src=\"https://img.shields.io/github/stars/Vitorian/awesome-fpga?style=social\"/\u003e : A collection of resources on FPGA devices and development in general.\r\n\r\n  - [kelu124/awesome-latticeFPGAs](https://github.com/kelu124/awesome-latticeFPGAs) \u003cimg src=\"https://img.shields.io/github/stars/kelu124/awesome-latticeFPGAs?style=social\"/\u003e : 📖 List of FPGA Lattice boards using open tools.\r\n\r\n  - [FPGA-Systems/fpga-awesome-list](https://github.com/FPGA-Systems/fpga-awesome-list) \u003cimg src=\"https://img.shields.io/github/stars/FPGA-Systems/fpga-awesome-list?style=social\"/\u003e : fpga-awesome-list. Полезные ресурсы по тематике FPGA / ПЛИС.\r\n\r\n  - [hdl/awesome](https://github.com/hdl/awesome) \u003cimg src=\"https://img.shields.io/github/stars/hdl/awesome?style=social\"/\u003e : A curated list of awesome resources for HDL design and verification.\r\n\r\n  - [vhdl/awesome-vhdl](https://github.com/vhdl/awesome-vhdl) \u003cimg src=\"https://img.shields.io/github/stars/vhdl/awesome-vhdl?style=social\"/\u003e : A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.\r\n\r\n  - [clin99/awesome-eda](https://github.com/clin99/awesome-eda) \u003cimg src=\"https://img.shields.io/github/stars/clin99/awesome-eda?style=social\"/\u003e : A curated list of EDA open source projects.\r\n\r\n  - [iDoka/awesome-fpga-boards](https://github.com/iDoka/awesome-fpga-boards) \u003cimg src=\"https://img.shields.io/github/stars/iDoka/awesome-fpga-boards?style=social\"/\u003e : List of Repurposed FPGA boards which getting Second life in DYI or Hobby projects.\r\n\r\n  - [TM90/awesome-hwd-tools](https://github.com/TM90/awesome-hwd-tools) \u003cimg src=\"https://img.shields.io/github/stars/TM90/awesome-hwd-tools?style=social\"/\u003e : A curated list of awesome open source hardware design tools.\r\n\r\n  - [qninth/awesome-digital-ic](https://github.com/qninth/awesome-digital-ic) \u003cimg src=\"https://img.shields.io/github/stars/qninth/awesome-digital-ic?style=social\"/\u003e : A collection of great digital IC project/tutorial/website etc..\r\n\r\n  - [emanueledelsozzo/awesome-fpga-programming](https://github.com/emanueledelsozzo/awesome-fpga-programming) \u003cimg src=\"https://img.shields.io/github/stars/emanueledelsozzo/awesome-fpga-programming?style=social\"/\u003e : A curated list of awesome languages and tools to program FPGAs.\r\n\r\n  - [fukatani/awesome-hdl](https://github.com/fukatani/awesome-hdl) \u003cimg src=\"https://img.shields.io/github/stars/fukatani/awesome-hdl?style=social\"/\u003e : A curated list of awesome HDL, libraries, typical implementation and references.\r\n\r\n  - [mikeroyal/VHDL-Guide](https://github.com/mikeroyal/VHDL-Guide) \u003cimg src=\"https://img.shields.io/github/stars/mikeroyal/VHDL-Guide?style=social\"/\u003e : A guide covering VHDL including the applications, libraries and tools that will make you a better and more efficient with VHDL development.\r\n\r\n  - [mikeroyal/Verilog-SystemVerilog-Guide](https://github.com/mikeroyal/Verilog-SystemVerilog-Guide) \u003cimg src=\"https://img.shields.io/github/stars/mikeroyal/Verilog-SystemVerilog-Guide?style=social\"/\u003e : Verilog/SystemVerilog Guide. A guide covering Verilog \u0026 SystemVerilog including the applications, libraries and tools that will make you a better and more efficient developer by having a better understanding of how hardware works on the lowest level.\r\n\r\n  - [analogdevicesinc/hdl](https://github.com/analogdevicesinc/hdl) \u003cimg src=\"https://img.shields.io/github/stars/analogdevicesinc/hdl?style=social\"/\u003e : HDL libraries and projects. [wiki.analog.com/resources/fpga/docs/hdl](https://wiki.analog.com/resources/fpga/docs/hdl)\r\n\r\n  - [analogdevicesinc/hdl](https://github.com/FPGAwars/apio) \u003cimg src=\"https://img.shields.io/github/stars/FPGAwars/apio?style=social\"/\u003e : 🌱 Open source ecosystem for open FPGA boards. [github.com/FPGAwars/apio/wiki](https://github.com/FPGAwars/apio/wiki)\r\n\r\n\r\n\r\n\r\n## Learning Resources\r\n\r\n\r\n  - [sipeed/TangPrimer-20K-example](https://github.com/sipeed/TangPrimer-20K-example) \u003cimg src=\"https://img.shields.io/github/stars/sipeed/TangPrimer-20K-example?style=social\"/\u003e : AIoT opensource hardware platform. TangPrimer-20K-example project.\r\n\r\n  - [BrunoLevy/learn-fpga](https://github.com/BrunoLevy/learn-fpga) \u003cimg src=\"https://img.shields.io/github/stars/BrunoLevy/learn-fpga?style=social\"/\u003e : About Learning FPGA, yosys, nextpnr, and RISC-V\r\n\r\n  - [WangXuan95/ZedBoard-Tutorial](https://github.com/WangXuan95/ZedBoard-Tutorial) \u003cimg src=\"https://img.shields.io/github/stars/WangXuan95/ZedBoard-Tutorial?style=social\"/\u003e : Vivado+PetaLinux 系统搭建教程 —— 基于 Zedboard.\r\n\r\n  - [WangXuan95/UniPlug-FPGA](https://github.com/WangXuan95/UniPlug-FPGA) \u003cimg src=\"https://img.shields.io/github/stars/WangXuan95/UniPlug-FPGA?style=social\"/\u003e : 体积小、低成本、易用、扩展性强的 FPGA 核心板。\r\n\r\n\r\n\r\n## Frameworks\r\n\r\n  - ### HDL Framework\r\n\r\n    - #### C HDL\r\n\r\n        - [LiteX](https://github.com/enjoy-digital/litex) \u003cimg src=\"https://img.shields.io/github/stars/enjoy-digital/litex?style=social\"/\u003e : The LiteX framework provides a convenient and efficient infrastructure to create FPGA Cores/SoCs, to explore various digital design architectures and create[full FPGA based systems](https://github.com/enjoy-digital/litex/wiki/Projects).\r\n\r\n\r\n    - #### Scala HDL\r\n\r\n        - [Chisel](https://github.com/chipsalliance/chisel) \u003cimg src=\"https://img.shields.io/github/stars/chipsalliance/chisel3?style=social\"/\u003e : Chisel: A Modern Hardware Design Language. [www.chisel-lang.org/](www.chisel-lang.org/)\r\n\r\n        - [SpinalHDL](https://github.com/SpinalHDL/SpinalHDL) \u003cimg src=\"https://img.shields.io/github/stars/SpinalHDL/SpinalHDL?style=social\"/\u003e : Scala based HDL.\r\n\r\n\r\n\r\n    - #### Rust HDL\r\n\r\n        - [Veryl](https://github.com/dalance/veryl) \u003cimg src=\"https://img.shields.io/github/stars/dalance/veryl?style=social\"/\u003e : Veryl: A Modern Hardware Description Language.\r\n\r\n        - [RustHDL](https://github.com/samitbasu/rust-hdl) \u003cimg src=\"https://img.shields.io/github/stars/samitbasu/rust-hdl?style=social\"/\u003e : A framework for writing FPGA firmware using the Rust Programming Language.\r\n\r\n        - [VHDL-LS/rust_hdl](https://github.com/VHDL-LS/rust_hdl) \u003cimg src=\"https://img.shields.io/github/stars/VHDL-LS/rust_hdl?style=social\"/\u003e : This repository contains a fast VHDL language server and analysis library written in Rust.\r\n\r\n        - [yupferris/kaze](https://github.com/yupferris/kaze) \u003cimg src=\"https://img.shields.io/github/stars/yupferris/kaze?style=social\"/\u003e : An [HDL](https://en.wikipedia.org/wiki/Hardware_description_language) embedded in Rust. kaze provides an API to describe Modules composed of Signals, which can then be used to generate Rust simulator code or Verilog modules.\r\n\r\n        - [dalance/sv-parser](https://github.com/dalance/sv-parser) \u003cimg src=\"https://img.shields.io/github/stars/dalance/sv-parser?style=social\"/\u003e : SystemVerilog parser library fully compliant with IEEE 1800-2017.\r\n\r\n        - [dalance/svls](https://github.com/dalance/svls) \u003cimg src=\"https://img.shields.io/github/stars/dalance/svls?style=social\"/\u003e : SystemVerilog language server.\r\n\r\n        - [dalance/svlint](https://github.com/dalance/svlint) \u003cimg src=\"https://img.shields.io/github/stars/dalance/svlint?style=social\"/\u003e : SystemVerilog linter.\r\n\r\n        - [vivekmalneedi/veridian](https://github.com/vivekmalneedi/veridian) \u003cimg src=\"https://img.shields.io/github/stars/vivekmalneedi/veridian?style=social\"/\u003e : A SystemVerilog Language Server.\r\n\r\n        - [zachjs/sv2v](https://github.com/zachjs/sv2v) \u003cimg src=\"https://img.shields.io/github/stars/zachjs/sv2v?style=social\"/\u003e : SystemVerilog to Verilog conversion.\r\n\r\n\r\n    - #### Python HDL\r\n\r\n        - [nMigen](https://github.com/amaranth-lang/amaranth) \u003cimg src=\"https://img.shields.io/github/stars/amaranth-lang/amaranth?style=social\"/\u003e : A modern hardware definition language and toolchain based on Python.\r\n\r\n        - [Migen](https://github.com/m-labs/migen) \u003cimg src=\"https://img.shields.io/github/stars/m-labs/migen?style=social\"/\u003e : A Python toolbox for building complex digital hardware.\r\n\r\n        - [MyHDL](https://github.com/myhdl/myhdl) \u003cimg src=\"https://img.shields.io/github/stars/myhdl/myhdl?style=social\"/\u003e : MyHDL is a free, open-source package for using Python as a hardware description and verification language.\r\n\r\n        - [Magma](https://github.com/phanrahan/magma/) \u003cimg src=\"https://img.shields.io/github/stars/phanrahan/magma?style=social\"/\u003e : Magma is a hardware design language embedded in python.\r\n\r\n        - [PyRTL](https://github.com/UCSBarchlab/PyRTL) \u003cimg src=\"https://img.shields.io/github/stars/UCSBarchlab/PyRTL?style=social\"/\u003e : PyRTL provides a collection of classes for pythonic register-transfer level design, simulation, tracing, and testing suitable for teaching and research.\r\n\r\n        - [Veriloggen](https://github.com/PyHDI/veriloggen) \u003cimg src=\"https://img.shields.io/github/stars/PyHDI/veriloggen?style=social\"/\u003e : Veriloggen: A Mixed-Paradigm Hardware Construction Framework.\r\n\r\n        - [HWT](https://github.com/Nic30/hwt) \u003cimg src=\"https://img.shields.io/github/stars/Nic30/hwt?style=social\"/\u003e : VHDL/Verilog/SystemC code generator, simulator API written in python/c++.\r\n\r\n        - [HDL21](https://github.com/dan-fritchman/Hdl21) \u003cimg src=\"https://img.shields.io/github/stars/dan-fritchman/Hdl21?style=social\"/\u003e : Analog Hardware Description Library in Python.\r\n\r\n\r\n\r\n\r\n\r\n\r\n## Applications\r\n\r\n\r\n  - ### FPGA Applications\r\n\r\n    - #### Processor Chip\r\n\r\n        - ##### CPU Chip\r\n\r\n            - ###### RISC-V Chip\r\n\r\n                - [XiangShan (香山)](https://github.com/OpenXiangShan/XiangShan) \u003cimg src=\"https://img.shields.io/github/stars/OpenXiangShan/XiangShan?style=social\"/\u003e : XiangShan (香山) is an open-source high-performance RISC-V processor project. \"Towards Developing High Performance RISC-V Processors Using Agile Methodology\". (**[MICRO 2022](https://ieeexplore.ieee.org/abstract/document/9923860/)**)\r\n\r\n                - [Rocket Chip](https://github.com/chipsalliance/rocket-chip) \u003cimg src=\"https://img.shields.io/github/stars/chipsalliance/rocket-chip?style=social\"/\u003e : Rocket Chip Generator 🚀. This repository contains the Rocket chip generator necessary to instantiate the RISC-V Rocket Core.\r\n\r\n                - [MoonbaseOtago/vroom](https://github.com/MoonbaseOtago/vroom) \u003cimg src=\"https://img.shields.io/github/stars/MoonbaseOtago/vroom?style=social\"/\u003e : VRoom! RISC-V CPU. A new high-end RISC-V implementation.\r\n\r\n                - [SpinalHDL/VexRiscv](https://github.com/SpinalHDL/VexRiscv) \u003cimg src=\"https://img.shields.io/github/stars/SpinalHDL/VexRiscv?style=social\"/\u003e : SpinalHDL/VexRiscv.\r\n\r\n                - [DarkRISCV](https://github.com/darklife/darkriscv) \u003cimg src=\"https://img.shields.io/github/stars/darklife/darkriscv?style=social\"/\u003e : opensouce RISC-V cpu core implemented in Verilog from scratch in one night!\r\n\r\n                - [stnolting/neorv32](https://github.com/stnolting/neorv32) \u003cimg src=\"https://img.shields.io/github/stars/stnolting/neorv32?style=social\"/\u003e : The NEORV32 RISC-V Processor. 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.\r\n\r\n                - [ZipCPU/zipcpu](https://github.com/ZipCPU/zipcpu) \u003cimg src=\"https://img.shields.io/github/stars/ZipCPU/zipcpu?style=social\"/\u003e : The Zip CPU is a small, light-weight, RISC CPU.\r\n\r\n                - [olofk/serv](https://github.com/olofk/serv) \u003cimg src=\"https://img.shields.io/github/stars/olofk/serv?style=social\"/\u003e : SERV - The SErial RISC-V CPU.\r\n\r\n                - [riscv-mcu/e203_hbirdv2](https://github.com/riscv-mcu/e203_hbirdv2) \u003cimg src=\"https://img.shields.io/github/stars/riscv-mcu/e203_hbirdv2?style=social\"/\u003e : The Ultra-Low Power RISC-V Core. [doc.nucleisys.com/hbirdv2](https://doc.nucleisys.com/hbirdv2/)\r\n\r\n                - [ultraembedded/riscv](https://github.com/ultraembedded/riscv) \u003cimg src=\"https://img.shields.io/github/stars/ultraembedded/riscv?style=social\"/\u003e : RISC-V CPU Core (RV32IM).\r\n\r\n                - [ultraembedded/biriscv](https://github.com/ultraembedded/biriscv) \u003cimg src=\"https://img.shields.io/github/stars/ultraembedded/biriscv?style=social\"/\u003e : 32-bit Superscalar RISC-V CPU.\r\n\r\n                - [WangXuan95/USTC-RVSoC](https://github.com/WangXuan95/USTC-RVSoC) \u003cimg src=\"https://img.shields.io/github/stars/ZipCPU/wbuart32?style=social\"/\u003e : An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。\r\n\r\n                - [FPGAwars/FLIX-V](https://github.com/FPGAwars/FLIX-V) \u003cimg src=\"https://img.shields.io/github/stars/FPGAwars/FLIX-V?style=social\"/\u003e : FLIX-V: FPGA, Linux and RISC-V.\r\n\r\n\r\n\r\n\r\n        - ##### GPU Chip\r\n\r\n            - [Ventus(承影)](https://github.com/THU-DSP-LAB/ventus-gpgpu) \u003cimg src=\"https://img.shields.io/github/stars/THU-DSP-LAB/ventus-gpgpu?style=social\"/\u003e : Ventus(承影) GPGPU. GPGPU processor supporting RISCV-V extension, developed with [Chisel](https://github.com/chipsalliance/chisel) HDL.\r\n\r\n            - [jbush001/NyuziProcessor](https://github.com/jbush001/NyuziProcessor) \u003cimg src=\"https://img.shields.io/github/stars/jbush001/NyuziProcessor?style=social\"/\u003e : Nyuzi is an experimental GPGPU processor focused on compute intensive tasks. It includes a synthesizable hardware design written in System Verilog, an instruction set emulator, an LLVM based C/C++ compiler, software libraries, and tests.\r\n\r\n\r\n\r\n\r\n\r\n    - #### IP Module\r\n\r\n\r\n        - ##### IP Generator\r\n\r\n            - [lnis-uofu/OpenFPGA](https://github.com/lnis-uofu/OpenFPGA) \u003cimg src=\"https://img.shields.io/github/stars/lnis-uofu/OpenFPGA?style=social\"/\u003e : The award-winning OpenFPGA framework is the first open-source FPGA IP generator with silicon proofs supporting highly-customizable FPGA architectures. OpenFPGA provides complete EDA support for customized FPGAs, including Verilog-to-bitstream generation and self-testing verification. OpenFPGA opens the door to democratizing FPGA technology and EDA techniques with agile prototyping approaches and constantly evolving EDA tools for chip designers and researchers. [openfpga.readthedocs.io/en/master/](openfpga.readthedocs.io/en/master/). \"OpenFPGA: An Open-Source Framework for Agile Prototyping Customizable FPGAs\". (**[IEEE Micro, 2020](https://ieeexplore.ieee.org/abstract/document/9098028/)**)\r\n\r\n\r\n\r\n        - ##### PCIe Module\r\n\r\n            - [WangXuan95/Xilinx-FPGA-PCIe-XDMA-Tutorial](https://github.com/WangXuan95/Xilinx-FPGA-PCIe-XDMA-Tutorial) \u003cimg src=\"https://img.shields.io/github/stars/WangXuan95/Xilinx-FPGA-PCIe-XDMA-Tutorial?style=social\"/\u003e : Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核。\r\n\r\n            - [Reconfigurable-Computing/Xilinx-FPGA-PCIe-XDMA-Tutorial](https://github.com/Reconfigurable-Computing/Xilinx-FPGA-PCIe-XDMA-Tutorial) \u003cimg src=\"https://img.shields.io/github/stars/Reconfigurable-Computing/Xilinx-FPGA-PCIe-XDMA-Tutorial?style=social\"/\u003e : Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核。\r\n\r\n            - [enjoy-digital/litepcie](https://github.com/enjoy-digital/litepcie) \u003cimg src=\"https://img.shields.io/github/stars/enjoy-digital/litepcie?style=social\"/\u003e : LitePCIe provides a small footprint and configurable PCIe core.\r\n\r\n            - [alexforencich/verilog-pcie](https://github.com/alexforencich/verilog-pcie) \u003cimg src=\"https://img.shields.io/github/stars/alexforencich/verilog-pcie?style=social\"/\u003e : Verilog PCI Express Components Readme.\r\n\r\n\r\n\r\n        - ##### DDR Module\r\n\r\n            - [ultraembedded/core_ddr3_controller](https://github.com/ultraembedded/core_ddr3_controller) \u003cimg src=\"https://img.shields.io/github/stars/ultraembedded/core_ddr3_controller?style=social\"/\u003e : A DDR3 memory controller in Verilog for various FPGAs.\r\n\r\n            - [WangXuan95/FPGA-DDR-SDRAM](https://github.com/WangXuan95/FPGA-DDR-SDRAM) \u003cimg src=\"https://img.shields.io/github/stars/WangXuan95/FPGA-DDR-SDRAM?style=social\"/\u003e : An AXI4-based DDR1 controller to realize mass, cheap memory for FPGA. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。\r\n\r\n            - [adibis/DDR2_Controller](https://github.com/adibis/DDR2_Controller) \u003cimg src=\"https://img.shields.io/github/stars/adibis/DDR2_Controller?style=social\"/\u003e : DDR2 memory controller written in Verilog.\r\n\r\n            - [BrianHGinc/BrianHG-DDR3-Controller](https://github.com/BrianHGinc/BrianHG-DDR3-Controller) \u003cimg src=\"https://img.shields.io/github/stars/BrianHGinc/BrianHG-DDR3-Controller?style=social\"/\u003e : DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size \u0026 cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs \u0026 TBs included.\r\n\r\n            - [someone755/ddr3-controller](https://github.com/someone755/ddr3-controller) \u003cimg src=\"https://img.shields.io/github/stars/someone755/ddr3-controller?style=social\"/\u003e : A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs.\r\n\r\n            - [WangXuan95/FPGA-DDR-SDRAM](https://github.com/WangXuan95/FPGA-DDR-SDRAM) \u003cimg src=\"https://img.shields.io/github/stars/WangXuan95/FPGA-DDR-SDRAM?style=social\"/\u003e : An AXI4-based DDR1 controller to realize mass, cheap memory for FPGA. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。\r\n\r\n\r\n\r\n\r\n\r\n\r\n        - ##### Ethernet Module\r\n\r\n        - [alexforencich/verilog-ethernet](https://github.com/alexforencich/verilog-ethernet) \u003cimg src=\"https://img.shields.io/github/stars/alexforencich/verilog-ethernet?style=social\"/\u003e : Verilog Ethernet components for FPGA implementation.\r\n\r\n\r\n\r\n        - ##### WIFI Module\r\n\r\n        - [openwifi](https://github.com/open-sdr/openwifi) \u003cimg src=\"https://img.shields.io/github/stars/open-sdr/openwifi?style=social\"/\u003e : open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software.\r\n\r\n\r\n\r\n        - ##### UART Module\r\n\r\n            - [ZipCPU/wbuart32](https://github.com/ZipCPU/wbuart32) \u003cimg src=\"https://img.shields.io/github/stars/ZipCPU/wbuart32?style=social\"/\u003e : A simple, basic, formally verified UART controller.\r\n\r\n            - [WangXuan95/Verilog-UART](https://github.com/WangXuan95/Verilog-UART) \u003cimg src=\"https://img.shields.io/github/stars/WangXuan95/Verilog-UART?style=social\"/\u003e : 3 independent modules for FPGA: UART receiver, UART transmitter, UART interactive debugger. 3个独立模块：UART接收器、UART发送器、UART交互式调试器。\r\n\r\n\r\n\r\n\r\n        - ##### USB Module\r\n\r\n            - [WangXuan95/FPGA-USB-Device](https://github.com/WangXuan95/FPGA-USB-Device) \u003cimg src=\"https://img.shields.io/github/stars/WangXuan95/FPGA-USB-Device?style=social\"/\u003e : An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-disk, USB-keyboard, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个FPGA普通IO，而不需要额外的接口芯片。\r\n\r\n\r\n\r\n        - ##### CAN-bus Module\r\n\r\n            - [WangXuan95/FPGA-CAN](https://github.com/WangXuan95/FPGA-CAN) \u003cimg src=\"https://img.shields.io/github/stars/WangXuan95/FPGA-CAN?style=social\"/\u003e : An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。\r\n\r\n\r\n        - ##### AXI Module\r\n\r\n            - [pulp-platform/axi](https://github.com/pulp-platform/axi) \u003cimg src=\"https://img.shields.io/github/stars/pulp-platform/axi?style=social\"/\u003e : AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication.\r\n\r\n\r\n\r\n        - ##### HDMI Module\r\n\r\n            - [hdl-util/hdmi](https://github.com/hdl-util/hdmi) \u003cimg src=\"https://img.shields.io/github/stars/hdl-util/hdmi?style=social\"/\u003e : Send video/audio over HDMI on an FPGA. [purisa.me/blog/hdmi-released/](https://purisa.me/blog/hdmi-released/)\r\n\r\n\r\n\r\n\r\n        - ##### SD-card Module\r\n\r\n            - [WangXuan95/FPGA-SDcard-Reader](https://github.com/WangXuan95/FPGA-SDcard-Reader) \u003cimg src=\"https://img.shields.io/github/stars/WangXuan95/FPGA-SDcard-Reader?style=social\"/\u003e : An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。\r\n\r\n\r\n            - [WangXuan95/FPGA-SDcard-Reader-SPI](https://github.com/WangXuan95/FPGA-SDcard-Reader-SPI) \u003cimg src=\"https://img.shields.io/github/stars/FPGA-SDcard-Reader-SPI?style=social\"/\u003e : An FPGA-based SD-card reader via SPI bus, which can read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器(通过SPI总线)，可以从FAT16或FAT32格式的SD卡中读取文件。\r\n\r\n\r\n            - [WangXuan95/FPGA-SDfake](https://github.com/WangXuan95/FPGA-SDfake) \u003cimg src=\"https://img.shields.io/github/stars/WangXuan95/FPGA-SDfake?style=social\"/\u003e : Imitate SDcard using FPGAs. 使用FPGA模拟(伪装) SD卡。\r\n\r\n\r\n\r\n\r\n\r\n        - ##### NFC Module\r\n\r\n        - [WangXuan95/FPGA-NFC](https://github.com/WangXuan95/FPGA-NFC) \u003cimg src=\"https://img.shields.io/github/stars/WangXuan95/FPGA-NFC?style=social\"/\u003e : Build an NFC (RFID) card reader using FPGA and simple circuit instead of RFID-specfic chip. 用FPGA+分立器件电路搭建一个NFC(RFID)读卡器，不需要专门的RFID芯片。\r\n\r\n\r\n\r\n\r\n\r\n        - ##### SATA Module\r\n\r\n            - [WangXuan95/FPGA-SATA-HBA](https://github.com/WangXuan95/FPGA-SATA-HBA) \u003cimg src=\"https://img.shields.io/github/stars/WangXuan95/FPGA-SATA-HBA?style=social\"/\u003e : A SATA host (HBA) core based on Xilinx FPGA with GTH. Easy to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器，用来读写硬盘。\r\n\r\n\r\n\r\n        - ##### DAC Module\r\n\r\n            - [WangXuan95/FPGA-DAC-R2R-PWM](https://github.com/WangXuan95/FPGA-DAC-R2R-PWM) \u003cimg src=\"https://img.shields.io/github/stars/WangXuan95/FPGA-DAC-R2R-PWM?style=social\"/\u003e : FPGA-based 14bit DAC with resistance network and PWM.\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n    - #### Camera Firmware\r\n\r\n        - [apertus-open-source-cinema/axiom-firmware](https://github.com/apertus-open-source-cinema/axiom-firmware) \u003cimg src=\"https://img.shields.io/github/stars/apertus-open-source-cinema/axiom-firmware?style=social\"/\u003e : AXIOM Beta Software. Firmware required to boot \u0026 operate the [apertus° AXIOM Beta Camera](https://www.apertus.org/axiom-beta). \"微信公众号「OpenFPGA」《[世界上最伟大的开源作品-基于FPGA的开源摄影机--Axiom Camera](https://mp.weixin.qq.com/s/MVLeBwgpCvKlrqwaNzv4dA)》\"。\r\n\r\n\r\n\r\n\r\n    - #### Spiking Neural Network\r\n\r\n        - [ChFrenkel/tinyODIN](https://github.com/ChFrenkel/tinyODIN) \u003cimg src=\"https://img.shields.io/github/stars/ChFrenkel/tinyODIN?style=social\"/\u003e : tinyODIN Low-Cost Digital Spiking Neural Network (SNN) Processor.\r\n\r\n        - [ChFrenkel/ODIN](https://github.com/ChFrenkel/ODIN) \u003cimg src=\"https://img.shields.io/github/stars/ChFrenkel/ODIN?style=social\"/\u003e : ODIN Spiking Neural Network (SNN) Processor.\r\n\r\n        - [ChFrenkel/ReckOn](https://github.com/ChFrenkel/ReckOn) \u003cimg src=\"https://img.shields.io/github/stars/ChFrenkel/ReckOn?style=social\"/\u003e : ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales.\r\n\r\n\r\n\r\n    - #### Convolutional Neural Network\r\n\r\n        - [Xilinx/Vitis-AI](https://github.com/Xilinx/Vitis-AI/tree/master/demo) \u003cimg src=\"https://img.shields.io/github/stars/Xilinx/Vitis-AI?style=social\"/\u003e : Vitis AI offers a unified set of high-level C++/Python programming APIs to run AI applications across edge-to-cloud platforms, including DPU for Alveo, and DPU for Zynq Ultrascale+ MPSoC and Zynq-7000. It brings the benefits to easily port AI applications from cloud to edge and vice versa. 10 samples in [VART Samples](https://github.com/Xilinx/Vitis-AI/tree/master/demo/VART) are available to help you get familiar with the unfied programming APIs. [Vitis-AI-Library](https://github.com/Xilinx/Vitis-AI/tree/master/demo/Vitis-AI-Library) provides an easy-to-use and unified interface by encapsulating many efficient and high-quality neural networks.\r\n\r\n        - [tensil-ai/tensil](https://github.com/tensil-ai/tensil) \u003cimg src=\"https://img.shields.io/github/stars/tensil-ai/tensil?style=social\"/\u003e : Open source machine learning accelerators. [www.tensil.ai](https://www.tensil.ai/)\r\n\r\n        - [19801201/SpinalHDL_CNN_Accelerator](https://github.com/19801201/SpinalHDL_CNN_Accelerator) \u003cimg src=\"https://img.shields.io/github/stars/19801201/SpinalHDL_CNN_Accelerator?style=social\"/\u003e : CNN accelerator implemented with Spinal HDL.\r\n\r\n        - [ZFTurbo/MobileNet-in-FPGA](https://github.com/ZFTurbo/MobileNet-in-FPGA) \u003cimg src=\"https://img.shields.io/github/stars/ZFTurbo/MobileNet-in-FPGA?style=social\"/\u003e : Generator of verilog description for FPGA MobileNet implementation.\r\n\r\n        - [MasLiang/CNN-On-FPGA](https://github.com/MasLiang/CNN-On-FPGA) \u003cimg src=\"https://img.shields.io/github/stars/MasLiang/CNN-On-FPGA?style=social\"/\u003e : This is the code of the CNN on FPGA.But this can only be used for reference at present for some files are write coarsly using ISE.\r\n\r\n        - [PipeCNN](https://github.com/doonny/PipeCNN) \u003cimg src=\"https://img.shields.io/github/stars/doonny/PipeCNN?style=social\"/\u003e : PipeCNN is an OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks (CNNs).\r\n\r\n\r\n\r\n\r\n\r\n    - #### Object Detection\r\n\r\n        - [dhm2013724/yolov2_xilinx_fpga](https://github.com/dhm2013724/yolov2_xilinx_fpga) \u003cimg src=\"https://img.shields.io/github/stars/dhm2013724/yolov2_xilinx_fpga?style=social\"/\u003e : YOLOv2 Accelerator in Xilinx's Zynq-7000 Soc(PYNQ-z2, Zedboard and ZCU102). (**[硕士论文 2019](https://kns.cnki.net/KCMS/detail/detail.aspx?dbcode=CMFD\u0026dbname=CMFDTEMP\u0026filename=1019228234.nh\u0026uid=WEEvREcwSlJHSldRa1FhdXNXaEhoOGhUTzA5T0tESzdFZ2pyR1NJR1ZBaz0=$9A4hF_YAuvQ5obgVAqNKPCYcEjKensW4IQMovwHtwkF4VYPoHbKxJw!!\u0026v=MjE5NTN5dmdXN3JBVkYyNkY3RzZGdFBQcTVFYlBJUjhlWDFMdXhZUzdEaDFUM3FUcldNMUZyQ1VSTE9lWnVkdUY=), [电子技术应用 2019](https://kns.cnki.net/KCMS/detail/detail.aspx?dbcode=CJFQ\u0026dbname=CJFDLAST2019\u0026filename=DZJY201908009\u0026uid=WEEvREcwSlJHSldRa1FhdXNXaEhoOGhUTzA5T0tESzdFZ2pyR1NJR1ZBaz0=$9A4hF_YAuvQ5obgVAqNKPCYcEjKensW4IQMovwHtwkF4VYPoHbKxJw!!\u0026v=MDU0NDJDVVJMT2VadWR1Rnl2Z1c3ck1JVGZCZDdHNEg5ak1wNDlGYllSOGVYMUx1eFlTN0RoMVQzcVRyV00xRnI=), [计算机科学与探索 2019](https://kns.cnki.net/KCMS/detail/detail.aspx?dbcode=CJFQ\u0026dbname=CJFDTEMP\u0026filename=KXTS201910005\u0026uid=WEEvREcwSlJHSldRa1FhdXNXaEhoOGhUTzA5T0tESzdFZ2pyR1NJR1ZBaz0=$9A4hF_YAuvQ5obgVAqNKPCYcEjKensW4IQMovwHtwkF4VYPoHbKxJw!!\u0026v=MjkwNzdXTTFGckNVUkxPZVp1ZHVGeXZnVzdyT0xqWGZmYkc0SDlqTnI0OUZZWVI4ZVgxTHV4WVM3RGgxVDNxVHI=)**)\r\n\r\n        - [Yu-Zhewen/Tiny_YOLO_v3_ZYNQ](https://github.com/Yu-Zhewen/Tiny_YOLO_v3_ZYNQ) \u003cimg src=\"https://img.shields.io/github/stars/Yu-Zhewen/Tiny_YOLO_v3_ZYNQ?style=social\"/\u003e : Implement Tiny YOLO v3 on ZYNQ. \"A Parameterisable FPGA-Tailored Architecture for YOLOv3-Tiny\". (**[ARC 2020](https://link.springer.com/chapter/10.1007/978-3-030-44534-8_25)**)\r\n\r\n        - [HSqure/ultralytics-pt-yolov3-vitis-ai-edge](https://github.com/HSqure/ultralytics-pt-yolov3-vitis-ai-edge) \u003cimg src=\"https://img.shields.io/github/stars/HSqure/ultralytics-pt-yolov3-vitis-ai-edge?style=social\"/\u003e : This demo is only used for inference testing of Vitis AI v1.4 and quantitative compilation of DPU. It is compatible with the training results of [ultralytics/yolov3](https://github.com/ultralytics/yolov3) v9.5.0 (it needs to use the model saving method of Pytorch V1.4).\r\n\r\n        - [mcedrdiego/Kria_yolov3_ppe](https://github.com/mcedrdiego/Kria_yolov3_ppe) \u003cimg src=\"https://img.shields.io/github/stars/mcedrdiego/Kria_yolov3_ppe?style=social\"/\u003e : Kria KV260 Real-Time Personal Protective Equipment Detection. \"Deep Learning for Site Safety: Real-Time Detection of Personal Protective Equipment\". (**[Automation in Construction 2020](https://www.sciencedirect.com/science/article/abs/pii/S0926580519308325)**)\r\n\r\n        - [xlsjdjdk/Ship-Detection-based-on-YOLOv3-and-KV260](https://github.com/xlsjdjdk/Ship-Detection-based-on-YOLOv3-and-KV260) \u003cimg src=\"https://img.shields.io/github/stars/xlsjdjdk/Ship-Detection-based-on-YOLOv3-and-KV260?style=social\"/\u003e : This is the entry project of the Xilinx Adaptive Computing Challenge 2021. It uses YOLOv3 for ship target detection in optical remote sensing images, and deploys DPU on the KV260 platform to achieve hardware acceleration.\r\n\r\n        - [Pomiculture/YOLOv4-Vitis-AI](https://github.com/Pomiculture/YOLOv4-Vitis-AI) \u003cimg src=\"https://img.shields.io/github/stars/Pomiculture/YOLOv4-Vitis-AI?style=social\"/\u003e : Custom YOLOv4 for apple recognition (clean/damaged) on Alveo U280 accelerator card using Vitis AI framework.\r\n\r\n        - [mkshuvo2/ZCU104_YOLOv3_Post_Processing](https://github.com/mkshuvo2/ZCU104_YOLOv3_Post_Processing) \u003cimg src=\"https://img.shields.io/github/stars/mkshuvo2/ZCU104_YOLOv3_Post_Processing?style=social\"/\u003e : Tensor outputs form Vitis AI Runner Class for YOLOv3.\r\n\r\n        - [puffdrum/v4tiny_pt_quant](https://github.com/puffdrum/v4tiny_pt_quant) \u003cimg src=\"https://img.shields.io/github/stars/puffdrum/v4tiny_pt_quant?style=social\"/\u003e : quantization for yolo with xilinx/vitis-ai-pytorch.\r\n\r\n        - [chanshann/LITE_YOLOV3_TINY_VITISAI](https://github.com/chanshann/LITE_YOLOV3_TINY_VITISAI) \u003cimg src=\"https://img.shields.io/github/stars/chanshann/LITE_YOLOV3_TINY_VITISAI?style=social\"/\u003e : LITE_YOLOV3_TINY_VITISAI.\r\n\r\n        - [LukiBa/zybo_yolo](https://github.com/LukiBa/zybo_yolo) \u003cimg src=\"https://img.shields.io/github/stars/LukiBa/zybo_yolo?style=social\"/\u003e : YOLO example implementation using Intuitus CNN accelerator on ZYBO ZYNQ-7000 FPGA board.\r\n\r\n        - [matsuda-slab/YOLO_ZYNQ_MASTER](https://github.com/matsuda-slab/YOLO_ZYNQ_MASTER) \u003cimg src=\"https://img.shields.io/github/stars/matsuda-slab/YOLO_ZYNQ_MASTER?style=social\"/\u003e : Implementation of YOLOv3-tiny on FPGA.\r\n\r\n        - [AramisOposich/tiny_YOLO_Zedboard](https://github.com/AramisOposich/tiny_YOLO_Zedboard) \u003cimg src=\"https://img.shields.io/github/stars/AramisOposich/tiny_YOLO_Zedboard?style=social\"/\u003e : tiny_YOLO_Zedboard.\r\n\r\n        - [FerberZhang/Yolov2-FPGA-CNN-](https://github.com/FerberZhang/Yolov2-FPGA-CNN-) \u003cimg src=\"https://img.shields.io/github/stars/FerberZhang/Yolov2-FPGA-CNN-?style=social\"/\u003e : A demo for accelerating YOLOv2 in xilinx's fpga PYNQ.\r\n\r\n        - [Prithvi-Velicheti/FPGA-Accelerator-for-TinyYolov3](https://github.com/Prithvi-Velicheti/FPGA-Accelerator-for-TinyYolov3) \u003cimg src=\"https://img.shields.io/github/stars/Prithvi-Velicheti/FPGA-Accelerator-for-TinyYolov3?style=social\"/\u003e : An FPGA-Accelerator-for-TinyYolov3.\r\n\r\n        - [ChainZeeLi/FPGA_DPU](https://github.com/ChainZeeLi/FPGA_DPU) \u003cimg src=\"https://img.shields.io/github/stars/ChainZeeLi/FPGA_DPU?style=social\"/\u003e : This project is to implement YOLO v3 on Xilinx FPGA with DPU.\r\n\r\n        - [xbdxwyh/yolov3_fpga_project](https://github.com/xbdxwyh/yolov3_fpga_project) \u003cimg src=\"https://img.shields.io/github/stars/xbdxwyh/yolov3_fpga_project?style=social\"/\u003e : yolov3_fpga_project.\r\n\r\n        - [ZLkanyo009/Yolo-compression-and-deployment-in-FPGA](https://github.com/ZLkanyo009/Yolo-compression-and-deployment-in-FPGA) \u003cimg src=\"https://img.shields.io/github/stars/ZLkanyo009/Yolo-compression-and-deployment-in-FPGA?style=social\"/\u003e : 基于FPGA量化的人脸口罩检测。\r\n\r\n        - [xiying-boy/yolov3-AX7350](https://github.com/xiying-boy/yolov3-AX7350) \u003cimg src=\"https://img.shields.io/github/stars/xiying-boy/yolov3-AX7350?style=social\"/\u003e : 基于HLS_YOLOV3的驱动文件。\r\n\r\n        - [himewel/yolowell](https://github.com/himewel/yolowell) \u003cimg src=\"https://img.shields.io/github/stars/himewel/yolowell?style=social\"/\u003e : A set of hardware architectures to build a co-design of convolutional neural networks inference at FPGA devices.\r\n\r\n        - [embedeep/Free-TPU](https://github.com/embedeep/Free-TPU) \u003cimg src=\"https://img.shields.io/github/stars/embedeep/Free-TPU?style=social\"/\u003e : Free TPU for FPGA with Lenet, MobileNet, Squeezenet, Resnet, Inception V3, YOLO V3, and ICNet. Deep learning acceleration using Xilinx zynq (Zedboard or ZC702 ) or kintex-7 to solve image classification, detection, and segmentation problem.\r\n\r\n        - [yarakigit/design_contest_yolo_change_ps_to_pl](https://github.com/yarakigit/design_contest_yolo_change_ps_to_pl) \u003cimg src=\"https://img.shields.io/github/stars/yarakigit/design_contest_yolo_change_ps_to_pl?style=social\"/\u003e : Converts pytorch yolo format weights to C header files for bare-metal (FPGA implementation).\r\n\r\n        - [adamgallas/fpga_accelerator_yolov3tiny](https://github.com/adamgallas/fpga_accelerator_yolov3tiny) \u003cimg src=\"https://img.shields.io/github/stars/adamgallas/fpga_accelerator_yolov3tiny?style=social\"/\u003e : fpga_accelerator_yolov3tiny.\r\n\r\n        - [ylk678910/tiny-yolov3-fpga](https://github.com/ylk678910/tiny-yolov3-fpga) \u003cimg src=\"https://img.shields.io/github/stars/ylk678910/tiny-yolov3-fpga?style=social\"/\u003e : Use an all-programmable SoC board to implement locating and tracking tasks. The hardware algorithm, a row-stationary-like strategy, can parallel calculate and reduce the storage buffer area on FPGA.\r\n\r\n        - [zhen8838/K210_Yolo_framework](https://github.com/zhen8838/K210_Yolo_framework) \u003cimg src=\"https://img.shields.io/github/stars/zhen8838/K210_Yolo_framework?style=social\"/\u003e : Yolo v3 framework base on tensorflow, support multiple models, multiple datasets, any number of output layers, any number of anchors, model prune, and portable model to K210 !\r\n\r\n        - [SEASKY-Master/SEASKY_K210](https://github.com/SEASKY-Master/SEASKY_K210) \u003cimg src=\"https://img.shields.io/github/stars/SEASKY-Master/SEASKY_K210?style=social\"/\u003e : K210 PCB YOLO.\r\n\r\n        - [SEASKY-Master/Yolo-for-k210](https://github.com/SEASKY-Master/Yolo-for-k210) \u003cimg src=\"https://img.shields.io/github/stars/SEASKY-Master/Yolo-for-k210?style=social\"/\u003e : Yolo-for-k210.\r\n\r\n        - [TonyZ1Min/yolo-for-k210](https://github.com/TonyZ1Min/yolo-for-k210) \u003cimg src=\"https://img.shields.io/github/stars/TonyZ1Min/yolo-for-k210?style=social\"/\u003e : keras-yolo-for-k210.\r\n\r\n        - [vseasky/yolo-for-k210](https://github.com/vseasky/yolo-for-k210) \u003cimg src=\"https://img.shields.io/github/stars/vseasky/yolo-for-k210?style=social\"/\u003e : Yolo-for-k210.\r\n\r\n        - [shilicon/kr260_robotic_arm](https://github.com/shilicon/kr260_robotic_arm) \u003cimg src=\"https://img.shields.io/github/stars/shilicon/kr260_robotic_arm?style=social\"/\u003e : A robotic arm controller design based on AMD/Xilinx KR260 FPGA dev-kit. 这是一个在AMD/Xilinx Kria KR260 FPGA板卡上实现机械臂抓取物体的工程。\r\n\r\n\r\n\r\n    - #### Visual SLAM\r\n\r\n        - [sdoira/U96-SLAM](https://github.com/sdoira/U96-SLAM) \u003cimg src=\"https://img.shields.io/github/stars/sdoira/U96-SLAM?style=social\"/\u003e : Visual SLAM on Ultra96-V2.\r\n\r\n\r\n\r\n\r\n    - #### Image Compression\r\n\r\n        - [WangXuan95/FPGA-JPEG-LS-encoder](https://github.com/WangXuan95/FPGA-JPEG-LS-encoder) \u003cimg src=\"https://img.shields.io/github/stars/WangXuan95/FPGA-JPEG-LS-encoder?style=social\"/\u003e : An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器，可实现高压缩率的无损/近无损图象压缩。\r\n\r\n        - [WangXuan95/FPGA-MPEG2-encoder](https://github.com/WangXuan95/FPGA-MPEG2-encoder) \u003cimg src=\"https://img.shields.io/github/stars/WangXuan95/FPGA-MPEG2-encoder?style=social\"/\u003e : FPGA-based high performance MPEG2 encoder for video compression. 基于 FPGA 的高性能 MPEG2 视频编码器，可实现视频压缩。\r\n\r\n        - [WangXuan95/UH-JLS](https://github.com/WangXuan95/UH-JLS) \u003cimg src=\"https://img.shields.io/github/stars/WangXuan95/UH-JLS?style=social\"/\u003e : FPGA-based Ultra-High Throughput JPEG-LS encoder, which provides lossless image compression. 一个超高性能的FPGA JPEG-LS编码器，用来进行无损图象压缩。\r\n\r\n\r\n\r\n\r\n\r\n\r\n    - #### Motor Control\r\n\r\n        - [WangXuan95/FPGA-FOC](https://github.com/WangXuan95/FPGA-FOC) \u003cimg src=\"https://img.shields.io/github/stars/FPGA-FOC?style=social\"/\u003e : FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。\r\n\r\n\r\n\r\n\r\n    - #### Fixed-point\r\n\r\n        - [WangXuan95/Verilog-FixedPoint](https://github.com/WangXuan95/Verilog-FixedPoint) \u003cimg src=\"https://img.shields.io/github/stars/Verilog-FixedPoint?style=social\"/\u003e : A Verilog fixed-point lib: custom bit width, arithmetic, converting to float, with single cycle \u0026 pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。\r\n\r\n\r\n\r\n\r\n\r\n\r\n\r\n## Blogs\r\n\r\n  - ### FPGA Blogs\r\n\r\n    - [bilibili「老石谈芯」| 微信公众号「老石谈芯」](https://space.bilibili.com/612932327)\r\n        - [2020-06-27，FPGA芯片在人工智能时代的独特优势](https://www.bilibili.com/video/BV1EK4y1s7wP/?spm_id_from=333.788)\r\n        - [2020-07-05，FPGA芯片发展的三个阶段](https://www.bilibili.com/video/BV1Q5411W7sW/?spm_id_from=333.788)\r\n        - [2020-08-10，什么是数据中心？](https://www.bilibili.com/video/BV1h54y1i7u3/?spm_id_from=333.999.0.0)\r\n        - [2020-09-20，【芯片科普】国产芯片的明显短板：FPGA](https://www.bilibili.com/video/BV1ih411X7QD/?spm_id_from=333.788)\r\n        - [2020-11-04，入行十年，我总结了这份FPGA学习路线：搞定这四点，你也能轻松进阶](https://www.bilibili.com/video/BV1aK4y1E7nc/?spm_id_from=333.788)\r\n        - [2020-11-30，芯片工程师的一天 | 我如何每天高效工作12小时](https://www.bilibili.com/video/BV1Fv411b7gs/?spm_id_from=333.999.0.0)\r\n        - [2020-12-27，想去一线大厂做FPGA芯片开发？这些是你该学的知识](https://www.bilibili.com/video/BV11y4y1i7Lv/?spm_id_from=333.788)\r\n        - [2021-01-11，【芯片前沿】英特尔的这个AI芯片，性能如何超过英伟达20倍？](https://www.bilibili.com/video/BV11U4y1x7hH/?spm_id_from=333.788)\r\n        - [2021-01-17，为什么我不需要一个“完美”的桌面？ | 附完整桌面设备清单](https://www.bilibili.com/video/BV1Jh411y7WS/?spm_id_from=333.999.0.0)\r\n        - [2021-03-07，这就是最棒的效率软件！如果不是，我倒想试试你的 | Notion使用技巧分享](https://www.bilibili.com/video/BV1aV411v7te/?spm_id_from=333.999.0.0)\r\n        - [2021-04-04，微软如何成为FPGA芯片的全球第一大客户 | 深度解析微软Catapult FPGA项目](https://www.bilibili.com/video/BV1ny4y1x7ix/?spm_id_from=333.788)\r\n        - [2021-04-26，【Vlog】芯片工程师休息的一天 | 高效放松身心的五个方法](https://www.bilibili.com/video/BV1GZ4y1F7z7/?spm_id_from=333.999.0.0)\r\n        - [2021-06-15，我用了两年，写了一本没有代码的芯片书](https://www.bilibili.com/video/BV1Zv411p74J/?spm_id_from=333.788)\r\n        - [2021-07-04，揭秘“香山”：高性能开源RISC-V处理器 | 对话中科院计算所包云岗研究员](https://www.bilibili.com/video/BV1Mf4y1b7hm/?spm_id_from=333.999.0.0)\r\n        - [2021-07-28，【芯片硬核】如何设计一个高性能CPU？](https://www.bilibili.com/video/BV1t341167VV/?spm_id_from=333.999.0.0)\r\n        - [2021-12-03，【芯片硬核】学习模数转换芯片ADC？这些是你该掌握的知识](https://www.bilibili.com/video/BV11r4y1Q7EJ/?spm_id_from=333.999.0.0)\r\n        - [2022-02-12，如何用Notion保持全年自律？你该试试这个原则](https://www.bilibili.com/video/BV1Gb4y177no/?spm_id_from=333.999.0.0)\r\n        - [2022-03-20，风口来了？一个视频讲透电子信息类所有专业/行业！](https://www.bilibili.com/video/BV1g44y1N7iQ/?spm_id_from=333.999.0.0)\r\n        - [2022-03-26，AMD天价收购赛灵思，竟是为了这个芯片？](https://www.bilibili.com/video/BV17L411A7Cw/?spm_id_from=333.788)\r\n        - [2022-11-25，第一次看到光刻机，竟然这样？！](https://www.bilibili.com/video/BV1Av4y1272D/?spm_id_from=333.999.0.0)\r\n        - [2022-12-11，用软件开发FPGA：机械臂设计保姆级教程+源码](https://www.bilibili.com/video/BV1se411P7Xv/?spm_id_from=333.788)\r\n        - [2023-04-21，聊聊我发的论文：如何将芯片验证速度提升4万倍？用FPGA！](https://www.bilibili.com/video/BV1Do4y1b7mC/?spm_id_from=333.999.0.0)\r\n        - [2019-01-28，什么是FPGA工程师的核心竞争力](https://mp.weixin.qq.com/s/tMl3GNRxqjY5IX36YhOY4w)\r\n        - [2020-02-28，FPGA最有影响力的25个研究成果 – 系统架构篇](https://mp.weixin.qq.com/s/2ctLcsJf9GifaRchpvoAug)\r\n        - [2020-03-02，FPGA20年最有影响力的25个研究成果 – 微架构篇](https://mp.weixin.qq.com/s/a0rGav-SFF-d7r2pe1tsJQ)\r\n        - [2020-11-09，入行10年后，我总结了这份FPGA学习路线](https://mp.weixin.qq.com/s/x_hTZQIxFsKmsaEn4DMUcQ)\r\n        - [2021-01-18，Stratix10 NX：超越GPU的人工智能时代“最强”FPGA？](https://mp.weixin.qq.com/s/Ftv0IDQ3rTpW85wGLwsSGw)\r\n        - [2021-07-20，芯片开发语言：Verilog在左，Chisel在右](https://mp.weixin.qq.com/s/EKzYUofPaN-3CDG8LEl4HA)\r\n        - [2021-10-30，我在隔离酒店，“做了”一个AI视觉加速器](https://mp.weixin.qq.com/s/chBWjUdBRRfZOSs74lWmNQ)\r\n        - [2021-12-16，未来的十年，是中国芯片行业的黄金十年](https://mp.weixin.qq.com/s/aCebZn6P0SDelZ1YkNDcDQ)\r\n        - [2022-02-14，你能教教我们，二本如何去中科院实习吗？](https://mp.weixin.qq.com/s/hteiQebZizHKJaVLvEx5_A)\r\n        - [2022-02-17，490亿刀！AMD收购赛灵思，动了谁的蛋糕？](https://mp.weixin.qq.com/s/A3OTAvVA_BiUghJ_X6lljQ)\r\n        - [2022-04-07，ACAP：不是FPGA，胜似FPGA](https://mp.weixin.qq.com/s/FvS9QkT7SV4pK4gc86vovg)\r\n        - [2022-05-18，裸辞回国+放弃百w年薪，我是不是疯了？](https://mp.weixin.qq.com/s/j100HqS__26h_zhUml5pQg)\r\n        - [2022-08-01，如何设计一个RISC-V处理器？](https://mp.weixin.qq.com/s/ordM_ITgTBW61RHGld1HAw)\r\n        - [2022-12-14，用软件开发FPGA：机械臂设计保姆级教程](https://mp.weixin.qq.com/s/s3rES6-aDKscRvVR2LZlAw)\r\n        - [2023-01-10，我的2022年度总结](https://mp.weixin.qq.com/s/BVkRQFBYZG4jBDmuQiTBoQ)\r\n        - [2023-04-09，ChatGPT爆火，为什么英伟达又赢麻了？](https://www.bilibili.com/video/BV1na4y1T732/?spm_id_from=333.999.0.0)\r\n        - [2023-04-25，芯片从业者：你们的好日子在后头](https://mp.weixin.qq.com/s/O4DoYkP5tHfxdZA783U81A)\r\n        - [2023-05-22，全网最深度分析：OPPO五百亿造芯梦碎，哲库是个错误吗？](https://www.bilibili.com/video/BV1az4y1b7cW/?spm_id_from=333.999.0.0)\r\n        - [2023-05-23，【万字长文】论OPPO哲库的倒下](https://mp.weixin.qq.com/s/3KKJTfVebz03JzkNhY3p3w)\r\n    - 微信公众号「OpenFPGA」\r\n        - [2022-01-14，谈谈Verilog和SystemVerilog简史，FPGA设计是否需要学习SystemVerilog](https://mp.weixin.qq.com/s/ARVI4NUXFNG540VLTfglcg)\r\n        - [2022-05-31，优秀的 Verilog/FPGA开源项目介绍（二十四）- 脉冲神经网络 (SNN)](https://mp.weixin.qq.com/s/-sCsRLK7uh5jZZ4FSc1t6g)\r\n        - [2023-01-06，优秀的 Verilog/FPGA开源项目介绍（三十六）-RISC-V（新增一）](https://mp.weixin.qq.com/s/cbgGrGdKS1tUBQc1j3Fhpw)\r\n        - [2023-01-30，从FPGA说起的深度学习（一）](https://mp.weixin.qq.com/s/oDmwGnVEaZvLSoSincjLFA)\r\n        - [2023-02-08，从FPGA说起的深度学习（二）](https://mp.weixin.qq.com/s/4faZFvilJjPJyjHnARF0og)\r\n        - [2023-02-15，从FPGA说起的深度学习（三）](https://mp.weixin.qq.com/s/ecSer6VrTAsh_6_J5jEidQ)\r\n        - [2023-03-02，从FPGA说起的深度学习（四）](https://mp.weixin.qq.com/s/cjObRscNt1rs-RMAqHbnTg)\r\n        - [2023-03-10，从FPGA说起的深度学习（五）](https://mp.weixin.qq.com/s/WoSe5hn_G-2jQU31lvd9SQ)\r\n        - [2023-04-12，从FPGA说起的深度学习（六）-任务并行性](https://mp.weixin.qq.com/s/P6M4nd-svjC95J9qIy_4yQ)\r\n        - [2023-04-17，从FPGA说起的深度学习（七）-循环并行化](https://mp.weixin.qq.com/s/xe-SHMNI8a5iH7jrkDB1pA)\r\n        - [2023-04-28，从FPGA说起的深度学习（八）-数据并行性](https://mp.weixin.qq.com/s/1B0QellaAcL_vXRpUNgUcg)\r\n        - [2023-05-06，从FPGA说起的深度学习（九）- 优化最终章](https://mp.weixin.qq.com/s/EyK6nO09FxzHFJTM7TjwTQ)\r\n        - [2023-05-10，从FPGA说起的深度学习（十）](https://mp.weixin.qq.com/s/5vCvRRyyPfm6TEa9TmEsww)\r\n        - [2023-03-13，在FPGA设计中怎么应用ChatGPT？](https://mp.weixin.qq.com/s/BvCFoAi9tAvSs4QS4BFRdA)\r\n        - [2023-03-17，卧槽，这才是最强Verilog刷题网站！](https://mp.weixin.qq.com/s/vRBxv3-2GOclFeELhdT62w)\r\n        - [2023-03-17，还在为没有项目做发愁？这几个神级开源网站，都是FPGA/IC项目](https://mp.weixin.qq.com/s/mbx8l6nRilcVOMjMQU7iUA)\r\n        - [2023-03-20，【国产FPGA】国产FPGA搭建图像处理平台](https://mp.weixin.qq.com/s/Azg69UrhiwKrRtgzaJlCZg)\r\n        - [2023-03-22，【开源硬件】FPGA PCIe加速卡开源硬件及例程（RIFFA\\XDMA\\HDMI\\SDI）介绍](https://mp.weixin.qq.com/s/t7gTzUN2Z6l_fGWyk0gODg)\r\n        - [2023-03-23，想用FPGA加速神经网络，这两个开源项目你必须要了解](https://mp.weixin.qq.com/s/n9GREgdKNyRrJy9-mSX8wg)\r\n        - [2023-03-27，ChatGPT推荐的开源项目，到底靠不靠谱？](https://mp.weixin.qq.com/s/_ERFebXaLUbF3EQs_ZyPIQ)\r\n        - [2023-03-31，牛客网发布了全新数字逻辑题库！会不会导致今年FPGA/IC行业更卷？！！](https://mp.weixin.qq.com/s/3aMAveRN6rakI30NuNydxQ)\r\n        - [2023-04-03，FPGA有哪些优质的带源码的IP开源网站?](https://mp.weixin.qq.com/s/-JdGJyUVznAHhqKyr_xM2A)\r\n        - [2023-04-06，世界上最伟大的开源作品-基于FPGA的开源摄影机--Axiom Camera](https://mp.weixin.qq.com/s/MVLeBwgpCvKlrqwaNzv4dA)\r\n        - [2023-04-19，基于 FPGA 的低成本、低延时成像系统](https://mp.weixin.qq.com/s/kSC5Y_0vpmMhy718PhUVsw)\r\n        - [2023-04-21，MIPI摄像头工程=7系列FPGA + OV5640(MIPI) + 15 分钟 + VITIS](https://mp.weixin.qq.com/s/h3hbl7pynhml2t4sOg9tHw)\r\n        - [2023-04-24，在 FPGA 上快速构建 PID 算法](https://mp.weixin.qq.com/s/ozFDxLCCqYkusHCbC0QajQ)\r\n        - [2023-04-24，Verilog“七宗罪”](https://mp.weixin.qq.com/s/mVcp4AJPXk7zmNfEjHNiBw)\r\n        - [2023-05-08，FPGA上的视觉 SLAM](https://mp.weixin.qq.com/s/S2wicdaN_3kkJbexLuQGMw)\r\n        - [2023-05-22，数字硬件建模SystemVerilog总结（完结篇）](https://mp.weixin.qq.com/s/9dHz9aqAM7WRaCUu4QYkpA)\r\n        - [2023-05-22，OpenFPGA系列文章总结](https://mp.weixin.qq.com/s/yea1JY2dVy1GqzAc66RRVA)\r\n    - 微信公众号「FPGA之旅」\r\n        - [2022-08-29，FPGA点亮LED灯](https://mp.weixin.qq.com/s/OtBMm6iy8jrpHAl-FUI7XA)\r\n        - [2022-08-29，FPGA实现按键模块](https://mp.weixin.qq.com/s/wgOKGlKHXeyX2FNhTRzfIA)\r\n        - [2022-08-29，FPGA实现UART串口通信](https://mp.weixin.qq.com/s/N_BaLoVY97LdoWiL8XlSNQ)\r\n        - [2022-08-16，FPGA实现串口多比特发送接收模块](https://mp.weixin.qq.com/s/-SgBkJTbW-nRkG_eqjatWQ)\r\n        - [2022-08-20，FPGA实现IIC协议](https://mp.weixin.qq.com/s/3qwZRqjHEZzj4V8uMo0T4g)\r\n        - [2022-08-29，FPGA实现数码管显示](https://mp.weixin.qq.com/s/mcT0rhKOOhjV5KOwDxi8zA)\r\n        - [2022-02-26，FPGA数字时钟](https://mp.weixin.qq.com/s/ZqE81Ciw8NHc0hu2FyvKzQ)\r\n        - [2022-08-30，FPGA实现DS18B20温度采集](https://mp.weixin.qq.com/s/medhKIQCo-KB904mXzwmpw)\r\n        - [2022-08-31，FPGA驱动OLED屏幕](https://mp.weixin.qq.com/s/HPubkS3-EVhbcsShtyBCIQ)\r\n        - [2022-09-04，串口上位机模拟OLED屏](https://mp.weixin.qq.com/s/_6IMXK_hM0udLnciTAc75A)\r\n        - [2022-09-06，FPGA驱动OLED显示字符](https://mp.weixin.qq.com/s/5EpWq_-2dbDlKml-shzmKQ)\r\n        - [2022-09-07，FPGA采集DHT11温湿度](https://mp.weixin.qq.com/s/D2uBEG6cA4Q9kqO6mWcsgA)\r\n        - [2022-09-08，FPGA在OLED上显示DHT11数据](https://mp.weixin.qq.com/s/MKEMUNB7Bvc40aBPHt6dJQ)\r\n        - [2022-09-14，FPGA解析红外遥控信号](https://mp.weixin.qq.com/s/8ozdSrNjoYQrfiQjhRhj_w)\r\n        - [2022-09-24，FPGA实现超声波测距](https://mp.weixin.qq.com/s/5YYTZtk8WSU25LwgbpiaTw)\r\n        - [2022-10-02，FPGA舵机驱动](https://mp.weixin.qq.com/s/j0fv2Lhz4myCcJ70tumDtA)\r\n        - [2022-10-06，FPGA驱动VGA显示屏](https://mp.weixin.qq.com/s/HFHb4kDVQe3cm93JKnVb5A)\r\n        - [2022-10-09，OV5640摄像头简介与SCCB时序](https://mp.weixin.qq.com/s/Yr4-88xnwLqQKpCXEa7ysQ)\r\n        - [2022-10-14，FPGA驱动OV5640上电及初始化](https://mp.weixin.qq.com/s/m0JAqdng35-FC8E5pItlQA)\r\n        - [2022-10-16，FPGA实现SDRAM控制器](https://mp.weixin.qq.com/s/gPttDvm6XVBrimx1AAKvhQ)\r\n        - [2022-10-22，串口VGA搭配SDRAM_FIFO显示图片](https://mp.weixin.qq.com/s/C5tK3S8KJL2hHQam-6E-sA)\r\n        - [2022-11-06，​FPGA实现Sobel算法进行边沿检测](https://mp.weixin.qq.com/s/aF0-jXrvwIva03-wX9Sh3Q)\r\n        - [2022-12-03，​FPGA的工作原理，一篇全掌握！](https://mp.weixin.qq.com/s/pE-M9acv_oiIyMnr0gAomw)\r\n        - [2023-05-20，​FPGA实现MPU6050姿态解算](https://mp.weixin.qq.com/s/9s5y4Z4jJcEK_vp5B84x0Q)\r\n    - 微信公众号「FPGA技术江湖」\r\n        - [2020-07-24，基于FPGA的单目内窥镜定位系统设计（上）](https://mp.weixin.qq.com/s/ASGphfySxZ0Nh2_D-11pcA)\r\n        - [2020-07-25，​基于FPGA的单目内窥镜定位系统设计（中）](https://mp.weixin.qq.com/s/P_SITtBMvUdjPaCQZYuGWw)\r\n        - [2020-07-26，基于FPGA的单目内窥镜定位系统设计（下）](https://mp.weixin.qq.com/s/sPPhouAym54zXdDNWYqZJg)\r\n        - [2023-02-12，​往期精选：基于FPGA的电子计算器系统设计（附代码）](https://mp.weixin.qq.com/s/SW1YBrB6ujVuAO3YjS1ywQ)\r\n        - [2023-02-14，​国产芯片生态图谱（2022最新版）](https://mp.weixin.qq.com/s/CJW3aARsnyHSc6Iw8eRLJg)\r\n        - [2023-04-21，​万能芯片 — FPGA](https://mp.weixin.qq.com/s/RVDMBGV605msuDbyGscf4Q)\r\n        - [2023-04-28，​为什么需要FPGA原型验证？](https://mp.weixin.qq.com/s/DafVnlzemBQojsorGJ0W5w)\r\n        - [2023-05-11，​基于FPGA的实时图像边缘检测系统设计（附代码）](https://mp.weixin.qq.com/s/28TuVKvuaTBV1cv37yNRCw)\r\n        - [2023-05-16，​基于FPGA的单目内窥镜定位系统设计（附代码）](https://mp.weixin.qq.com/s/D0_AIic00y4y1Ice0iUsTA)\r\n        - [2023-05-18，​基于FPGA的CAN总线控制器的设计](https://mp.weixin.qq.com/s/myvp55su7TltPGTYwMZuaQ)\r\n        - [2023-05-22，基于FPGA的以太网控制器（MAC）设计](https://mp.weixin.qq.com/s/i7yXX3M-kn7nGLI_9LTzSw)\r\n        - [2023-05-23，如何在 FPGA 中做数学运算](https://mp.weixin.qq.com/s/N0kc-hrOTDywgfwy6SQ6JA)\r\n    - 微信公众号「疯狂的FPGA」\r\n        - [2023-03-09，《FPGA图像加速》第二章-bilibili回播入口](https://mp.weixin.qq.com/s/GEKZkMgKLYlhMSR6TCyUhQ)\r\n        - [2023-04-11，国内唯一的纯FPGA论坛，发布](https://mp.weixin.qq.com/s/a6vliiR-XOftaBA-r6fGYw)\r\n        - [2023-04-21，从入门到放弃，坚持一年时间很难](https://mp.weixin.qq.com/s/O2Cv3qIOnkA8Qhgg6r9o4w)\r\n    - 微信公众号「FPGA探索者」\r\n        - [2023-04-06，往年FPGA、数字IC实习秋招面试汇总贴 + 复习建议，收藏！](https://mp.weixin.qq.com/s/mAs857VDUrUtLA2fytlT9A)\r\n    - 微信公众号「FPGA之家」\r\n        - [2023-01-20，FPGA相关知识系统介绍](https://mp.weixin.qq.com/s/WF6uofAdSzMRPeEZ029KLQ)\r\n        - [2023-04-23，Xilinx FPGA的约束设计和时序分析总结](https://mp.weixin.qq.com/s/aZHdhqwzlREjXwg8Sjq2oA)\r\n        - [2023-04-28，FPGA设计原则总结](https://mp.weixin.qq.com/s/rBGuQR0OlmfkKXf3rVHCbw)\r\n    - 微信公众号「深蓝AI」\r\n        - [2023-04-05，稚晖君的机器人创业团队招聘](https://mp.weixin.qq.com/s/zu0JMOdWYk79YRMdr1Q3gg)\r\n    - 微信公众号「AIIC Xidian」\r\n        - [2022-10-16，研读|基于FPGA脉冲神经网络模型设计与实现](https://mp.weixin.qq.com/s/kkFeerMgtdnj--7AoOHV4A)\r\n        - [2023-05-18，研读|基于FPGA的卷积神经网络交通信号灯分类的设计与实现](https://mp.weixin.qq.com/s/UX-d2RdXeR6KtwmFEjshTA)\r\n    - 微信公众号「FPGA设计论坛」\r\n        - [2023-03-08，未来的高性能FPGA是否会优于GPU？](https://mp.weixin.qq.com/s/-UvhpvHid8GwzC4y5_WTLg)\r\n        - [2023-04-22，FPGA与处理器技术的的应用领域](https://mp.weixin.qq.com/s/k9JeLNyHVkQfIBPmEzVtdw)\r\n        - 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