{"id":3663,"url":"https://github.com/drom/awesome-hdl","name":"awesome-hdl","description":"Hardware Description Languages","projects_count":137,"last_synced_at":"2026-08-06T14:00:22.280Z","repository":{"id":37670670,"uuid":"88018788","full_name":"drom/awesome-hdl","owner":"drom","description":"Hardware Description Languages","archived":false,"fork":false,"pushed_at":"2026-07-09T02:37:45.000Z","size":184,"stargazers_count":1162,"open_issues_count":0,"forks_count":109,"subscribers_count":58,"default_branch":"master","last_synced_at":"2026-07-18T07:03:49.989Z","etag":null,"topics":["awesome","awesome-list","hacktoberfest","hardware-description-language","hdl","verilog","vhdl"],"latest_commit_sha":null,"homepage":"","language":null,"has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/drom.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null,"notice":null,"maintainers":null,"copyright":null,"agents":null,"dco":null,"cla":null}},"created_at":"2017-04-12T06:43:44.000Z","updated_at":"2026-07-15T23:04:52.000Z","dependencies_parsed_at":"2023-02-14T11:31:39.254Z","dependency_job_id":"dc18a9a5-d13b-43ea-829f-03eb5c53fa2a","html_url":"https://github.com/drom/awesome-hdl","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/drom/awesome-hdl","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/drom%2Fawesome-hdl","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/drom%2Fawesome-hdl/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/drom%2Fawesome-hdl/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/drom%2Fawesome-hdl/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/drom","download_url":"https://codeload.github.com/drom/awesome-hdl/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/drom%2Fawesome-hdl/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":36338379,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-08-06T04:43:03.162Z","status":"ssl_error","status_checked_at":"2026-08-06T04:43:02.660Z","response_time":54,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"created_at":"2024-01-06T00:46:06.406Z","updated_at":"2026-08-06T14:00:22.281Z","primary_language":null,"list_of_lists":false,"displayable":true,"categories":["HDL doc","HDL simulators and compilers","Meta HDL and Transpilers","HLS","Other HDL languages","Hardware Intermediate Representations","Visualization and Documentation generators","License","PSS : Portable test and Stimulus Standard","Synthesis tools","HDL parsers","Other Simulation tools","Other Design Automation tools","HDL Libraries"],"sub_categories":[],"readme":"# Awesome Hardware Description Languages\n\nA curated list of amazingly awesome hardware description language projects.\n\n\n# Hardware development\n\n## HDL doc\n\n* Verilog [IEEE Std 1364-2001](https://inst.eecs.berkeley.edu/~cs150/fa06/Labs/verilog-ieee.pdf), [Quick Ref Guide](http://sutherland-hdl.com/pdfs/verilog_2001_ref_guide.pdf), [SystemVerilog 3.1a](http://www.ece.uah.edu/~gaede/cpe526/SystemVerilog_3.1a.pdf), [Synthesizing SystemVerilog Busting the Myth that SystemVerilog is only for Verification](http://sutherland-hdl.com/papers/2013-SNUG-SV_Synthesizable-SystemVerilog_paper.pdf)\n* VHDL standards [IEEE Std 1076-2000](http://edg.uchicago.edu/~tang/VHDLref.pdf)\n* SystemC standards [IEEE Std 1666-2011](http://paginas.fe.up.pt/~ee07166/lib/exe/fetch.php?media=1666-2011.pdf)\n\n\n## HDL simulators and compilers\n\n   * Verilog\n      - [Verilator](https://www.veripool.org/wiki/verilator) Verilog to C++ transpiler\n      - [Icarus Verilog](http://iverilog.icarus.com/) - simulator\n      - [Yosys](http://www.clifford.at/yosys/) - RTL synthesis\n   * VHDL\n      * [nvc](https://github.com/nickg/nvc) - GPLv3 VHDL compiler and simulator, IEEE 1076-2002, written in C\n      * [GHDL](https://github.com/ghdl/ghdl) - VHDL compiler and simulator, IEEE 1076-2002, written in ADA\n   * chisel/firrtl\n      * [essent](https://github.com/ucsc-vama/essent) - firrtl to optimized C++ transpiler\n      * [treadle](https://github.com/chipsalliance/treadle) - firrtl simulator written in Scala\n   * [Lola-2](https://inf.ethz.ch/personal/wirth/Lola/Lola2.pdf)\n      - [Oberon-2013](https://inf.ethz.ch/personal/wirth/Lola/) - Project Oberon, 2013 Edition, written in [Oberon-07](http://www-oldurls.inf.ethz.ch/personal/wirth/Oberon/) [License](https://inf.ethz.ch/personal/wirth/ProjectOberon/license.txt)\n   * CIRCT\n      * [ksim](https://github.com/pku-liang/ksim) - CIRCT IR to optimized C++ transpiler\n      * [arcilator](https://github.com/circt/arc-tests) - Fast and cycle-accurate hardware simulation in CIRCT\n    \n## HDL Libraries\n\n* VHDL\n  - [Open Logic](https://github.com/open-logic/open-logic) - VHDL Standard Library (FIFOs, CDCs, fixed-point math, etc.)\n* System Verilog\n  - [Taxi Transport Library](https://github.com/fpganinja/taxi) - System Verilog standard library\n\n## Meta HDL and Transpilers\n\n* C++\n   - [SystemC](https://www.doulos.com/knowhow/systemc/) - an IEEE standard meta-HDL\n   - [VisualHDL](http://sysprogs.com/legacy/visualhdl/) - an integrated development environment (IDE) rapid design for FPGAs\n\n* Dart\n   - [ROHD](https://github.com/intel/rohd) - A framework for hardware description and verification, 2021+\n\n* Haskell\n   - [concat](https://github.com/conal/concat) Haskell to hardware, 2016+\n   - https://github.com/conal/talk-2015-haskell-to-hardware\n   - [CλaSH](https://github.com/clash-lang/clash-compiler) - A functional hardware description language\n   - [pipelineDSL](https://github.com/p12nGH/pipelineDSL) - A Haskell DSL for describing hardware pipelines\n   - [Bluespec](https://github.com/B-Lang-org/bsc) - Compiler, simulator, and tools for the Bluespec Hardware Description Language.\n   - [sv2v](https://github.com/zachjs/sv2v) - SystemVerilog to Verilog conversion\n\n* Java\n   - [jhdl](http://www.jhdl.org/) ..2006\n   - [PSHDL](http://pshdl.org/)\n\n* JavaScript\n   - [reqack](https://github.com/drom/reqack) -  elastic circuit toolchain\n   - [hdl-js](https://github.com/DmitrySoshnikov/hdl-js) - Hardware description language (HDL) parser, and Hardware simulator.\n   - [shdl](https://github.com/jcbuisson/shdl) - Simple Hardware Description Language\n   - [irtl](https://github.com/drom/irtl) - a small intermediate representation (IR) builder for RTL. emits FIRRTL or Verilog\n\n* Julia\n   - [Julia-Verilog](https://github.com/interplanetary-robot/Verilog.jl) - a Verilog-generation DSL for Julia., 2017\n\n* OCaml\n   - [Hardcaml](https://github.com/janestreet/hardcaml/blob/master/docs/index.mdx) An OCaml library for designing hardware, complete with testing and simulation tools.\n\n* Kotlin\n  - [Verik](https://github.com/frwang96/verik) HDL for design and verification. generates SV. UVM.\n\n* Python\n  - [HWT](https://github.com/Nic30/hwt) Meta HDL, verification env. IP-core generator, analysis tools, HDL glue\n  - [garnet](https://github.com/StanfordAHA/garnet) Coarse-Grained Reconfigurable Architecture generator based on magma, 2018+\n  - [magma](https://github.com/phanrahan/magma/) - Meta HDL, 2017+\n  - [migen](https://github.com/m-labs/migen) - Meta HDL, 2011+\n  - [Amaranth](https://github.com/amaranth-lang/amaranth) (previously nMigen) - A refreshed Python toolbox for building complex digital hardware, 2018+\n  - [MyHDL](https://github.com/myhdl/myhdl) - Process based HDL, verification framework included, 2004+\n  - [Pyrope](https://masc.soe.ucsc.edu/pyrope.html) - Python-like language supporting \"fluid pipelines\" and \"live flow\", 2017+\n  - [PyRTL](https://github.com/UCSBarchlab/PyRTL) - Meta HDL, simulator suitable for research.\n  - [PyMTL](https://github.com/cornell-brg/pymtl) - Process based HDL, verification framework included, 2014+\n  - [veriloggen](https://github.com/PyHDI/veriloggen) - Python, Verilog centric meta HDL with HLS like features, 2015-?\n  - [Hdl21](https://github.com/dan-fritchman/Hdl21) - Analog HDL in Python\n  - [PyHGL](https://github.com/PyHGL/pyhgl) - Meta HDL, three-state event-driven simulation, 2022+\n  - [GateForge](https://github.com/vagran/GateForge) - Meta HDL, 2025+\n  - [PyXHDL](https://github.com/davidel/pyxhdl) - Python Frontend For VHDL And Verilog, 2023+\n\n* Ruby\n   - [RHDL](https://github.com/philtomson/RHDL)\n\n* Rust\n   - [Filament](https://filamentHDL.com) - Fearless Hardware Design\n   - [hoodlum](https://github.com/tcr/hoodlum) - Meta HDL, 2016+\n   - [kaze](https://github.com/yupferris/kaze) - Meta HDL, 2019+\n   - [calyx](https://github.com/cucapra/calyx) - Intermediate Language (IL) for Hardware Accelerator Generators, 2020+\n   - [Spade](https://gitlab.com/spade-lang/spade) - A hardware description language inspired by modern software languages like Rust.\n   - [Cement](https://github.com/pku-liang/Cement) - A rule-based Meta HDL inspired by Bluespec, 2024+\n\n* Scala\n   - [chisel](https://github.com/freechipsproject/chisel3) - Meta HDL, 2012+\n   - [SpinalHDL](https://github.com/SpinalHDL/SpinalHDL) - Meta HDL 2012+\n   - [DFHDL](https://dfianthdl.github.io/) - Multi-abstraction Meta HDL, 2021+\n\n* C#\n   - [Quokka](https://github.com/EvgenyMuryshkin/qusoc) - C# to low-level RTL translator (Verilog, VHDL) and simulation toolkit examples (gates, components, RISC-V, SoC)\n\n* Veryl\n   - [Veryl](https://github.com/dalance/veryl) - An original HDL based on SystemVerilog / Rust syntax, and transplier to SystemVerilog\n\n## HLS\n\n* [hlslibs](https://github.com/hlslibs) - ac_math, ac_dsp, ac_types\n* [legup](http://legup.eecg.utoronto.ca/) - 2011-2015, LLVM based c-\u003everilog\n* [bambu](http://panda.dei.polimi.it/?page_id=31) - 2003-?, GCC based c-\u003everilog\n* [augh](http://tima.imag.fr/sls/research-projects/augh/) - c-\u003everilog, DSP support\n* https://github.com/utwente-fmt - abstract hls, verification libraries\n* [Shang](https://github.com/etherzhhb/Shang) - 2012-2014, LLVM based, c-\u003everilog\n* [xronos](https://github.com/endrix/xronos) - 2012, java, simple HLS\n* [Potholes](https://github.com/SamuelBayliss/Potholes) - 2012-2014 - polyhedral model preprocessor, Uses Vivado HLS, PET\n* [hls_recurse](https://github.com/m8pple/hls_recurse) - 2015-2016 - conversion of recursive fn. for stackless architectures\n* [hg_lvl_syn](https://github.com/funningboy/hg_lvl_syn) - 2010, ILP, Force Directed scheduler\n* [abc](https://people.eecs.berkeley.edu/~alanmi/abc/) \u003c2008-?, A System for Sequential Synthesis and Verification\n* [polyphony](https://github.com/ktok07b6/polyphony) - 2015-2017, simple python to hdl\n* [DelayGraph](https://github.com/ni/DelayGraph) - 2016, C#, register assignment algorithms\n* [ahaHLS](https://github.com/dillonhuff/ahaHLS) - 2019, An open source high level synthesis (HLS) tool using LLVM\n* [combinatorylogic/soc](https://github.com/combinatorylogic/soc) - 2019, An experimental System-on-Chip with a custom compiler toolchain.\n* [Quokka](https://github.com/EvgenyMuryshkin/QuokkaEvaluation) - C# to HL RTL translator\n* [Vitis](https://github.com/Xilinx/HLS) - LLVM based, made by Xilinx. [user manual](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug1399-vitis-hls.pdf)\n* [XLS](https://google.github.io/xls/) - 2020, HLS toolchain from Google\n* [hector](https://github.com/pku-liang/Hector) - 2022, An open-source hardware synthesis framework using MLIR\n* [Holoso](https://github.com/Zubax/holoso) - 2026+, high-level synthesis of portable Verilog from idiomatic Python for numerical/DSP applications\n\n\n## Other HDL languages\n\n* [act](https://github.com/asyncvlsi/act) - asynchronous circuit/compiler tools\n* [autopiper](https://github.com/google/autopiper)\n* [ORD](https://github.com/tub-msc/ordec) - Python-superset HDL for analog and mixed-signal IC design entry, part of the open-source ORDeC design platform\n* [Silice](https://github.com/sylefeb/Silice) - A language for hardcoding algorithms into FPGA hardware\n* [TL-Verilog](https://makerchip.com) - 2015+, Supports \"timing-abstract\" and \"transaction-level design\" methodologies; supported by proprietary and open-source tools\n* [AnvilHDL](https://github.com/kisp-nus/anvil) - 2025+, An HDL designed to help avoid common bugs while allowing low-level control through a Rust-like type system\n\n\n## Hardware Intermediate Representations\n\n* [CIRCT](https://circt.llvm.org) - 2020+, LLVM / MLIR framework \"Circuit IR Compilers and Tools\"\n* [coreir](https://github.com/rdaly525/coreir) - 2016-?, LLVM HW compiler## License\n* [lgraph](https://github.com/masc-ucsc/lgraph) - 2017-?, A Multi-Language Synthesis and Simulation IR for Hardware Design\n* [firrtl](https://github.com/freechipsproject/firrtl) - 2016-?, Flexible Intermediate Representation for RTL\n* [LLHD](https://github.com/fabianschuiki/llhd) - Low Level Hardware Description — A foundation for building hardware design tools\n* [SpyDrNet](https://byuccl.github.io/spydrnet/) - 2019+, Framework for parsing and manipulating structural netlists in Python\n* [VLSIR](https://github.com/Vlsir/Vlsir) - IC Interchange Formats, defined in Google Protobuf SDL\n\n## Synthesis tools\n\n* [vtr-verilog-to-routing](https://github.com/verilog-to-routing/vtr-verilog-to-routing)\n* [yosys](https://github.com/YosysHQ/yosys) - RTL synthesis framework\n\n\n## Visualization and Documentation generators\n\n* [bitfield](https://github.com/drom/bitfield) - Javascript bit field diagram renderer\n* [d3-wave](https://github.com/Nic30/d3-wave) - Javascript wave graph visualizer for RTL simulations\n* [d3-hwschematic](https://github.com/Nic30/d3-hwschematic) - Javascript hierarchical schematic visualizer for HDLs\n* [wavedrom](https://github.com/drom/wavedrom) - Javascript wave graph visualizer for documentations and sim.\n* [netlistsvg](https://github.com/nturley/netlistsvg) - Javascript schematic visualizer\n* [sphinx-hwt](https://github.com/Nic30/sphinx-hwt) - Plugin for sphinx documentation generator which adds schematic into html documentation.\n* [Visual Debug](https://redwoodeda.com/viz) - Custom simulation visualization framework, available within the [Makerchip.com](https://makerchip.com) IDE.\n\n\n## HDL parsers\n\n* [hdlConvertor](https://github.com/Nic30/hdlConvertor) - Fast (System) Verilog/VHDL parser written as C++ extension for Python\n* [pyVHDLParser](https://github.com/Paebbels/pyVHDLParser) - VHDL parser written in Python\n* [rust_hdl](https://github.com/kraigher/rust_hdl) - VHDL parser and language server written in Rust\n* [sv-parser](https://github.com/dalance/sv-parser) -  IEEE 1800-2017 System Verilog Parser written in Rust\n* [verible](https://chipsalliance.github.io/verible/) - Verible provides a SystemVerilog parser, style-linter, and formatter.\n* [slang](https://github.com/MikePopoloski/slang) - SystemVerilog compiler and language service.\n* [pyverilog](https://github.com/PyHDI/Pyverilog) - Python-based Hardware Design Processing Toolkit for Verilog HDL\n* [Surelog](https://github.com/chipsalliance/Surelog) - SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API.\n\n## Other Simulation tools\n\n* [midas](https://github.com/ucb-bar/midas) - FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL\n* [cocotb](https://github.com/potentialventures/cocotb) - A coroutine based co-simulation library for writing VHDL and Verilog testbenches in Python\n* [osvvm](https://github.com/OSVVM/OsvvmLibraries) -  A VHDL verification framework, verification utility library, verification component library, and a simulator independent scripting flow\n* [uvvm](https://github.com/OSVVM/OsvvmLibraries) - A free and Open Source Methodology and Library for VHDL verification of FPGA and ASIC.\n* [crave](https://github.com/antmicro/crave) - Constrained random stimuli generation for C++ and SystemC (AntMicro's fork of [crave](https://github.com/agra-uni-bremen/crave))\n\n## Other Design Automation tools\n\n* [peakrdl](https://github.com/SystemRDL/PeakRDL) - CSR toolchain to generate RTL, UVM RAL models, document(html and markdown), IPXACT, c header from SystemRDL or IPXACT.\n* [RgGen](https://github.com/rggen/rggen) - Code generator tool to generate RTL, UVM RAL models and Wiki documents from CSR specifications\n* [sv-tests](https://symbiflow.github.io/sv-tests) - Test suite designed to check compliance with the SystemVerilog standard\n* [tbengy](https://github.com/prasadp4009/tbengy) - Code generator tool to generate SV/UVM RTL and Testbech as well scripts with support for bitstream generation for Digilent FPGAs\n* [HDLGen](https://github.com/WilsonChen003/HDLGen) - Tool for processing of embedded Perl or Python scripts in Verilog source code.\n* [fusesoc](https://github.com/olofk/fusesoc) -  Package manager and a set of build tools for HDL.\n* [bender](https://github.com/pulp-platform/bender) -  Dependency management tool for hardware design projects.\n* [hbs](https://github.com/m-kru/hbs) - A lean dependency management and build system for hardware description projects.\n* [svlint](https://github.com/dalance/svlint) - SystemVerilog linter compliant with IEEE1800-2017. Written in Rust, based on [sv-parser](https://github.com/dalance/sv-parser).\n\n## PSS : Portable test and Stimulus Standard\n\n* [Accellera](https://www.accellera.org/downloads/standards/portable-stimulus) - specification to create a single representation of stimulus and test scenarios\n* [PSS 2.1 LRM](https://www.accellera.org/images/downloads/standards/pss/Portable_Test_Stimulus_Standard_v2.1.pdf) - PDF Spec\n* [PSSTools Org](https://github.com/PSSTools) - PSS releated tools on GitHub. Parsers, editor plugins.\n* [Matthew Ballance](https://github.com/mballance) PSS Blog posts:\n   - [Automating Bare-Metal Tests with PSS](https://bitsbytesgates.com/pss/2023/02/25/AutomatingBareMetalTestsWithPSS.html)\n   - [PSS Fundamentals: Actions, Components, and Test Generation](https://bitsbytesgates.com/pss/2023/03/03/ActionsComponents_and_TestGeneration.html)\n   - [Declarative Programming and Multi-Core Tests](https://bitsbytesgates.com/pss/2023/03/11/DeclarativeMultiCoreTests.html)\n   - [Relating Actions with Dataflow](https://bitsbytesgates.com/pss/2023/03/18/RelatingActionsWithDataflow.html)\n   - [Modeling DMA Test Scenarios with PSS](https://bitsbytesgates.com/pss/2023/03/25/ModelingTestScenariosForDMA.html)\n   - [PSS Memory Management Fundamentals](https://bitsbytesgates.com/pss/2023/04/02/ManagingMemoryInPSS.html)\n   - [PSS Concurrency and Resources](https://bitsbytesgates.com/pss/2023/04/09/PSSConcurrencyAndResources.html)\n   - [Interacting with Devices via PSS Registers](https://bitsbytesgates.com/pss/2023/04/18/InteractingWithDevicesViaRegisters.html)\n   - [Relating Actions with Dataflow Part2 -- Parallelism](https://bitsbytesgates.com/pss/2023/05/07/RelatingActionsWithDataflowPart2.html)\n* [PSS CookBook](https://github.com/LeeKaiXuan/PSS_Cookbook) - Documentation for introducing the usage of PSS language\n\n\n## License\n\n[![CC0](cc-zero.svg)](https://creativecommons.org/publicdomain/zero/1.0/)\n\nTo the extent possible under law, [Aliaksei Chapyzhenka](http://drom.io) has waived all copyright and related or neighboring rights to this work.\n","projects_url":"https://awesome.ecosyste.ms/api/v1/lists/drom%2Fawesome-hdl/projects"}