{"id":113837,"url":"https://github.com/pythonlinks/awesome-gatemate","name":"awesome-gatemate","description":"A Curated Directory of Awesome Cologne Chips' GateMate FPGA Links.","projects_count":65,"last_synced_at":"2026-06-18T08:00:20.385Z","repository":{"id":271001843,"uuid":"912120725","full_name":"PythonLinks/awesome-gatemate","owner":"PythonLinks","description":"A Curated Directory of Awesome Cologne Chips' GateMate FPGA Links.","archived":false,"fork":false,"pushed_at":"2026-02-21T05:38:06.000Z","size":35,"stargazers_count":24,"open_issues_count":0,"forks_count":0,"subscribers_count":3,"default_branch":"main","last_synced_at":"2026-06-01T16:04:57.018Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"","language":null,"has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/PythonLinks.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null,"notice":null,"maintainers":null,"copyright":null,"agents":null,"dco":null,"cla":null}},"created_at":"2025-01-04T16:56:47.000Z","updated_at":"2026-05-29T16:19:36.000Z","dependencies_parsed_at":"2026-02-06T00:00:41.260Z","dependency_job_id":null,"html_url":"https://github.com/PythonLinks/awesome-gatemate","commit_stats":null,"previous_names":["pythonlinks/awesome-gatemate"],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/PythonLinks/awesome-gatemate","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/PythonLinks%2Fawesome-gatemate","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/PythonLinks%2Fawesome-gatemate/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/PythonLinks%2Fawesome-gatemate/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/PythonLinks%2Fawesome-gatemate/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/PythonLinks","download_url":"https://codeload.github.com/PythonLinks/awesome-gatemate/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/PythonLinks%2Fawesome-gatemate/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":34481331,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-05-26T15:22:16.424Z","status":"online","status_checked_at":"2026-06-18T02:00:06.871Z","response_time":128,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"created_at":"2026-01-26T22:20:08.416Z","updated_at":"2026-06-18T08:00:20.386Z","primary_language":null,"list_of_lists":false,"displayable":true,"categories":["FirmWare","A Curated Directory of Awesome Cologne Chips' GateMate FPGA Links.","Documentation","Boards","Pricing","GateWare","Hardware Testing","Design Tools","Videos","Articles","Social Media"],"sub_categories":[],"readme":"## A Curated Directory of Awesome Cologne Chips' GateMate FPGA Links.\n\n[Why GateMate Video](https://www.youtube.com/embed/ZokT2tEiXSA)    [Slides](https://pythonlinks.info/presentations/vectors/WhyGateMate.pdf)\n\n## Documentation\n\n[Documentation]()[GateMate FPGA | Cologne Chip](https://colognechip.com/programmable-logic/gatemate/#tab-313423).  Scroll down and click on the documentation tab.  The data sheet is very well writen.  Installation guide is also there.  If you want to understand LUT trees, make sure to read the primitives library. \n\n[Architectural Slides](https://colognechip.com/wp-content/uploads/Novel-GateMate-FPGA-Architecture-FPL2021.pdf)  Really these slides should be in the data sheet. [Video](https://underline.io/lecture/34046-novel-architecture-for-european-fpga)\n\n[Serdes Slides 2025](https://colognechip.com/docs/presentations/gatemate-serdes-fpgaconf2025.pdf)\n\n[Radiation Tolerance Slides 2025](https://colognechip.com/docs/presentations/gatemate-radiation-fpgaconf2025.pdf) \n\n[Seot 2025 Cern Talk](https://indico.cern.ch/event/1587509/contributions/6690211/attachments/3140818/5574499/gatemate-fdf2025.pdf)\n\n[Project Peppercorn - GateMate FPGA Bitstream Documentation](https://github.com/YosysHQ/prjpeppercorn)  Placement flow is a modified [HeAP](https://ieeexplore.ieee.org/document/6339278). [CRoute](https://ieeexplore.ieee.org/document/8735564) does the routing, followed by simulated annealing.   \n\n[LUT-Tree Analsysis](https://github.com/chili-chips-ba/openCologne/tree/main/8.StressTest#lut-tree-logic) An excellent explanation of the LUT trees. \n\n[Playground for various GateMate FPGA SerDes loopback tests](https://github.com/pu-cc/gm_serdes_lb)\n\n[Interface Guide for Peripheral Devices with 3.3 V Signaling](https://www.colognechip.com/docs/ug1003-gatemate1-level-shifting-latest.pdf)\n\n[LUTRAM_Stress_Test capacities](https://github.com/tarik-ibrahimovic/LUTRAM_Stress_Test)\n\n[Phased Locked Loop (PLL) Implementation](https://colognechip.com/wp-content/uploads/c3-pll-white-paper.pdf) \n\n[ToolChain(https://colognechip.com/programmable-logic/gatemate/#tab-313424)\n\n## Boards\n\n[Olimex GateMateA1-EVB1](https://www.olimex.com/Products/FPGA/GateMate/GateMateA1-EVB/) This 50€ board is the popular choice for starting with the GateMate. You can buy a case from Olimex, or [print your own](https://www.printables.com/model/1591329-olimex-gatematea1-evb-case) You will probably want to use at lease one of these [extension boards](https://github.com/intergalaktik/Extension_Boards_for_Olimex_GateMate). Here is the list of [UEXT Extension boards](https://www.olimex.com/Products/Modules/UEXT/). At [the bottom of this page]([pico-ice: Using Pmods](https://pico-ice.tinyvision.ai/md_pmods.html)) is a list of lists of pMods. \n\n[Cologne Chip's GateMate FPGA Evaluation Board](https://www.colognechip.com/programmable-logic/gatemate-evaluation-board/)  This is the board made by Cologne Chips. [\\$398 at Digikey](https://www.digikey.com.au/en/products/detail/cologne-chip/CCGM1A1-E1/16087880)\n\n[Prototyping board for the GateMate Evaluation Board](https://github.com/fm4dd/gm-proto-e1)\n\n[GMM-7550](https://www.gmm7550.dev/doc/hardware.html)  [2024 Feb FOSDEM Talk](https://archive.fosdem.org/2024/schedule/event/fosdem-2024-2107-cologne-chip-gatemate-fpga-filling-a-gap-between-hardware-and-software-with-a-presentation-of-the-gmm-7550-module-/) Includes a Raspberry Pi hat, an I/O Breakout board, a USB3.0 interface and a  memory module which provides [512Kx8 static RAM]([CY7C1049GN30-10ZSXI - Infineon Technologies](https://www.infineon.com/cms/en/product/memories/sram-static-ram/asynchronous-sram/cy7c1049gn30-10zsxi/)) with 10 ns access time and 16 MiB QSPI NOR FLASH (S25LP128-JBLE).\n[Trenz Electonics # FPGA module](https://shop.trenz-electronic.de/de/TEG2000-01-P001-FPGA-Modul-mit-GateMate-A1-von-Cologne-Chip-16-MByte-QSPI-Flash-4-x-5-cm#)     16 MByte QSPI Flash, 4 x 5 cm]. 82.11 € (69.00 € net).     \n\n[Sipeed Tang PMOD DVI](https://wiki.sipeed.com/hardware/en/tang/tang-PMOD/FPGA_PMOD.html)) (Scroll down to 5.1) is a module for HDMI output/input, which requires the use of LVDS differential pairs.  It works with the GateMate ColorBar DVI demo on the Cologne Chips eval circuit board.  The only change needed is to replace [this line](https://github.com/trabucayre/GateMate_demos/blob/main/colorBarDVI/colorBarDVI.v#L21 ) with ``A({~TMDS_0_clk, ~TMDS_0_data}),```. Does not work with the Olimex board, it seems to have an issue with the level shifters.  Thanks @gwenhaelgoavec.\n\n[ULX5M](https://www.chili-chips.xyz/open-cologne/) is in development.  It will be in the popular Raspberry Pi Compute Module 4 (CM4) form-factor, so it can attach to lots of different base boards. \n\n[LED Matrix](https://github.com/Martoni/Martoni_Pcb_collection/tree/main/glm5va) A little PCB to adapt 2.5v GateMate signals to 5V for matrix Led.\n\n## Pricing\n\nOne user told me that the 21€ Gatemate A1 board compares very roughly, to Lattice ECP5-5G LFE5UM5G-45 [53€-83€ at digikey,com](https://www.digikey.ie/en/products/filter/fpgas-field-programmable-gate-array/696?s=N4IgTCBcDaIDIDECiBWAqgWRQcQLQBYUEQBdAXyA), or AMD's Spartan 6 (XC6SLX45T, In Europe Lattice and AMD also face import duties, and a greater risk of supply chain disruptions, particularly if the chips are made in Taiwan.\n\n## FirmWare\n\n[JTag Programmer](https://github.com/phdussud/pico-dirtyJtag) Also supports Uart. \n\n[GGMM-7550/gmm7550-control-rp2040](https://github.com/GMM-7550/gmm7550-control-rp2040) Circuit Python control of the GateMate FPGA for the gmm7550 board. \n\n## GateWare\n\n[Space Inavders on an Intel 8080.  Article](https://olimex.wordpress.com/2025/01/08/space-inavders-retrogame-runs-on-gatematea1-evb/)   [GitLab](https://gitlab.com/x653/spaceinvaders-fpga)\n\n[Open Cologne](https://www.chili-chips.xyz/open-cologne)  is a project to expand the GateMate ecosystem,  funded by the EU.  [Github](https://github.com/chili-chips-ba/openCologne) \n\n[Integrated Logic Analyzer](https://www.cnx-software.com/2024/06/11/gatemate-integrated-logic-analyzer-ila-deep-dive/) allows you to capture and analyze all signals of your design as a waveform directly within the FPGA. [Video](https://www.youtube.com/watch?v=TZblFccw4kg\u0026t=23s)   [GitHub](https://github.com/colognechip/gatemate_ila)\n\n[FemtoRV Tutorial](https://github.com/fm4dd/gatemate-riscv)\n[Litex VexRisc](https://github.com/YosysHQ/prjpeppercorn-test-cases/tree/main/058-litex-vexriscv)\n\n[Litex FazyRV RISC-V](https://github.com/YosysHQ/prjpeppercorn-test-cases/tree/main/089-litex-fazyrv)  1 2 or 4 or maybe 8 bit RISC-V processor. \n\n[Litex Serv](https://github.com/YosysHQ/prjpeppercorn-test-cases/tree/main/061-litex-serv) An award winning one bit RISC-V serial processor.\n\n[NEORV32 on GateMate Issues ](https://github.com/stnolting/neorv32/discussions/983) NEORV has a big enphasis on useability and realiability. \n\n[EduBoss](https://fpga-ignite.github.io/presentations-pdf/presentation16.pdf) written by people very active in the GateMate community. \n\n[PCIe on GateMate NLnet Project](https://github.com/chili-chips-ba/openCologne-PCIE)\n\n[NLnet; USB 3](https://nlnet.nl/project/GateMate-USB3-PHY/)\n\n## Hardware Testing\n\nThe [Project Peppercorn GateMate Test Cases](https://github.com/YosysHQ/prjpeppercorn-test-cases/tree/main), has a large amount of useful code for testing the hardware.  These gateware tests are good starting points for controlling the hardware. \n\n[1080p @ 60Hz capable HDMI interface](https://elektronaut.tech/en/fpga/driving-full-hd-video-with-the-cologne-chip-gatemate-fpga/) using a dedicated TMDS interface IC\n\n[OV7670 Camera Controller](https://github.com/YosysHQ/prjpeppercorn-test-cases/tree/main/107-ov7670)\n\nVGA Tests: [color](https://github.com/YosysHQ/prjpeppercorn-test-cases/tree/main/011-vga-color)   [Image](https://github.com/YosysHQ/prjpeppercorn-test-cases/tree/main/041-vga-image), and 16 more, too many to index, just [search the page]((https://github.com/YosysHQ/prjpeppercorn-test-cases/tree/main))\n[Button Test](https://github.com/YosysHQ/prjpeppercorn-test-cases/tree/main/022-buttons) \n\nOLED Tests: [color](https://github.com/YosysHQ/prjpeppercorn-test-cases/tree/main/031-oled-color) [sprite](https://github.com/YosysHQ/prjpeppercorn-test-cases/tree/main/032-oled-sprite) [pong-wall](https://github.com/YosysHQ/prjpeppercorn-test-cases/tree/main/033-oled-wall) \n[DVI Colorbar](https://github.com/YosysHQ/prjpeppercorn-test-cases/tree/main/072-dvi-lvds) Verical bars on the screen.\n[PS2 port](https://github.com/YosysHQ/prjpeppercorn-test-cases/tree/main/080-ps2) (Keyboard or mouse)\n[Serdes](https://github.com/YosysHQ/prjpeppercorn-test-cases/tree/main/084-serdes-loopback)\n[ColecoVision Console](https://github.com/YosysHQ/prjpeppercorn-test-cases/tree/main/085-colecovision) \n\n[St7789 OLED](https://github.com/YosysHQ/prjpeppercorn-test-cases/tree/main/096-oled-st7789)\n\n[Litexx I2C](https://github.com/YosysHQ/prjpeppercorn-test-cases/tree/main/097-litex-with-i2c)\n[OPL2 Audio Synthesizer](https://docs.icebreaker-fpga.org/hardware/pmod/dvi/)\n\n[HyperRAM](https://github.com/YosysHQ/prjpeppercorn-test-cases/tree/main/101-litex-hyperram)\n\n[SDCard](https://github.com/YosysHQ/prjpeppercorn-test-cases/tree/main/102-litex-sdcard)\n[Ethernet](https://github.com/YosysHQ/prjpeppercorn-test-cases/tree/main/103-litex-eth)\n\n[PSRAM](https://github.com/YosysHQ/prjpeppercorn-test-cases/tree/main/104-psram)\n[SPI Flash](https://github.com/YosysHQ/prjpeppercorn-test-cases/tree/main/105-litex-spi-flash)\n\n[DVI Driver](https://github.com/YosysHQ/prjpeppercorn-test-cases/tree/main/099-dvi-12b) for the 12 bit Black Mesa Labs DVI PMOD\n\n[OV7670 Camera](https://github.com/YosysHQ/prjpeppercorn-test-cases/tree/main/107-ov7670)\n\n## Design Tools\n\n[DI-FEntwumS](https://elektronikforschung.de/projekte/di-fentwums) (In German) Open source design and visualization environment for dynamically configurable microchips\n\n## Videos\n\n[Novel Architecture for European FPGA](https://underline.io/lecture/34046-novel-architecture-for-european-fpga) An introduction to the GateMate architecture.  [Slides](https://colognechip.com/wp-content/uploads/Novel-GateMate-FPGA-Architecture-FPL2021.pdf)\n\n## Articles\n\n[Accelerating the Game of Life with the GateMate FPGA: Computing 960 Cells in a Single Clock Cycle](https://www.linkedin.com/pulse/game-life-fpga-40x24-grid-computed-single-clock-cycle-dave-fohrn-ajhxe/) This is a great example of using the GateMate small adders in an innovateive way. \n\n[Using One and Two Bit Adders](https://forth.pythonlinks.info/using-gatemate-1-and-2-bit-adders) to solve the above game of life calculations. Not as efficient a solution, but easy to understand.\n\n[GateMate FPGA Tool Chain](https://www.adiuvoengineering.com/post/gatemate-fpga-tool-chain)\n\n[Cologne Chips GateMate FPGA Offers a Flexible Architecture](https://www.hackster.io/news/cologne-chip-s-gatemate-fpga-offers-a-flexible-cologne-programmable-element-architecture-2db40691dded)\n\n[Would you buy a $20 GateMate FPGA from Germany’s Cologne Chip?](https://www.eejournal.com/article/would-you-buy-a-20-gatemate-fpga-from-germanys-cologne-chip/)\n\n[Why GateMate?](https://forth.pythonlinks.info/why-i-am-using-the-gatemate-fpga) compares the GateMate to other FPGAs.\n\n## Social Media\n\n[OLIMEX Gatemate Board Discord Channel](https://discord.gg/5ahf3Rc46j)\n\n[Radiona Gatemate Discord Channel]([radiona](https://discord.gg/BSJfFz2H3g)) They are making the Olimex Gagemate add on boards, and [OpenCologne and the ULX5S](https://www.chili-chips.xyz/open-cologne/).\n\n[@olimex@mastodon.social](https://mastodon.social/@olimex) makers of the leading Gatemate board. \n\n[@PythonLinks@mastodon.social](https://mastodon.social/@PythonLinks) maintains this directory.\n\nI encourage everyone to minimise your useage of corporate social media such as X/Twitter and [join the fediverse](https://JoinMastodon.org).   \n","projects_url":"https://awesome.ecosyste.ms/api/v1/lists/pythonlinks%2Fawesome-gatemate/projects"}