{"id":1751,"url":"https://github.com/qninth/awesome-digital-ic","name":"awesome-digital-ic","description":"A collection of great digital IC project/tutorial/website etc..","projects_count":87,"last_synced_at":"2026-09-20T14:00:30.708Z","repository":{"id":41100754,"uuid":"482511115","full_name":"qninth/awesome-digital-ic","owner":"qninth","description":"A collection of great digital IC project/tutorial/website etc..","archived":false,"fork":false,"pushed_at":"2022-05-10T15:43:05.000Z","size":1484,"stargazers_count":163,"open_issues_count":0,"forks_count":6,"subscribers_count":1,"default_branch":"main","last_synced_at":"2026-08-31T20:09:11.638Z","etag":null,"topics":["asic","awesome","awesome-list","digital-ic","fpga"],"latest_commit_sha":null,"homepage":"","language":null,"has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/qninth.png","metadata":{},"created_at":"2022-04-17T12:00:50.000Z","updated_at":"2026-08-16T18:54:59.000Z","dependencies_parsed_at":"2022-07-16T05:30:47.326Z","dependency_job_id":null,"html_url":"https://github.com/qninth/awesome-digital-ic","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/qninth/awesome-digital-ic","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/qninth%2Fawesome-digital-ic","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/qninth%2Fawesome-digital-ic/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/qninth%2Fawesome-digital-ic/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/qninth%2Fawesome-digital-ic/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/qninth","download_url":"https://codeload.github.com/qninth/awesome-digital-ic/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/qninth%2Fawesome-digital-ic/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":341189360,"owners_count":37530254,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-08-22T15:14:58.755Z","status":"online","status_checked_at":"2026-09-20T02:00:06.856Z","response_time":61,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"created_at":"2024-01-04T18:14:30.518Z","updated_at":"2026-09-20T14:00:30.709Z","primary_language":null,"list_of_lists":false,"displayable":true,"categories":["Awesome Awesome ⭐","Tools","Tutorials and Courses 💬[Intro](./Tutorials%20and%20Courses/README.md)","Games","Projects and IPs","Forums","Online Judge Platforms"],"sub_categories":["FPGA","HDL","Build a CPU","web","Quora Topics","Communication Technology","Information Technology","Verification","Mobile Phone","PC"],"readme":"# Awesome Digital IC\n\n\u003e A collection of great ASIC/FPGA/VLSI project/tutorial/website.\n\n- 🚩 = Chinese\n- 📍 = Github Project\n- 📽 = With vedio\n- 👶 = Easy to get start with\n- ⭐ = Recommended\n- 💬 = More Details\n\n## Awesome Awesome ⭐\n\n\u003e Awesome-lists for digital ic.\n\n- [FPGA Tutorial](https://github.com/LeiWang1999/FPGA) 📍![stars](https://img.shields.io/github/stars/LeiWang1999/FPGA) - A curated list of amazingly FPGA tutorials and projects.\n- [Awesome Hardware Description Languages](https://github.com/drom/awesome-hdl) 📍![stars](https://img.shields.io/github/stars/drom/awesome-hdl) - A curated list of amazingly awesome hardware description language projects.\n- [Awesome FPGA](https://github.com/Vitorian/awesome-fpga) 📍![stars](https://img.shields.io/github/stars/Vitorian/awesome-fpga) - A collection of resources on FPGA devices and development in general.\n- [Open Hardware Verification](https://github.com/ben-marshall/awesome-open-hardware-verification) 📍![stars](https://img.shields.io/github/stars/ben-marshall/awesome-open-hardware-verification) - A curated List of Free and Open Source hardware verification tools and frameworks.\n- [Awesome Open Source EDA Projects](https://github.com/clin99/awesome-eda) 📍![stars](https://img.shields.io/github/stars/clin99/awesome-eda) - A curated list of EDA open source projects. \n- [List of FPGA boards](https://github.com/iDoka/awesome-fpga-boards) 📍![stars](https://img.shields.io/github/stars/iDoka/awesome-fpga-boards) - List of Repurposed FPGA boards.\n- [awesome-hwd-tools](https://github.com/TM90/awesome-hwd-tools) 📍![stars](https://img.shields.io/github/stars/TM90/awesome-hwd-tools) - A curated list of awesome open source hardware design tools with a focus on chip design.\n- [Awesome Electronics](https://github.com/kitspace/awesome-electronics) 📍![stars](https://img.shields.io/github/stars/kitspace/awesome-electronics) - A curated list of awesome resources for electronic engineers and hobbyists.\n- [Awesome Lattice FPGA boards](https://github.com/kelu124/awesome-latticeFPGAs) 📍![stars](https://img.shields.io/github/stars/kelu124/awesome-latticeFPGAs) - A curated list of awesome open-source FPGA boards\n\n### Github Topics\n\n- [verilog](https://github.com/topics/verilog?o=desc\u0026s=stars) 📍 - Here are 2,566 public repositories matching \"verilog\" topic...\n- [vhdl](https://github.com/topics/vhdl?o=desc\u0026s=stars) 📍- Here are 1,766 public repositories matching \"vhdl\" topic...\n- [fpga](https://github.com/topics/fpga?o=desc\u0026s=stars) 📍 - Here are 3,136 public repositories matching \"fpga\" topic...\n\n### Quora Topics\n\n- [verilog](https://github.com/topics/verilog?o=desc\u0026s=stars) 📍 - Here are 2,566 public repositories matching \"verilog\" topic...\n- [vhdl](https://github.com/topics/vhdl?o=desc\u0026s=stars) 📍- Here are 1,766 public repositories matching \"vhdl\" topic...\n- [fpga](https://github.com/topics/fpga?o=desc\u0026s=stars) 📍 - Here are 3,136 public repositories matching \"fpga\" topic...\n\n## Projects and IPs\n\n- [OpenCores](https://opencores.org/) ⭐ - Free and open source IP cores.\n- [FreeCores](http://freecores.github.io/) 📍![stars](https://img.shields.io/github/stars/freecores/freecores.github.io) - A home for open source hardware cores, a fork of almost all cores that was once on OpenCores.org.\n- [Must-have verilog systemverilog modules](https://github.com/pConst/basic_verilog) 📍![stars](https://img.shields.io/github/stars/pConst/basic_verilog) - A collection of verilog systemverilog synthesizable modules.\n- [fpga4fun](https://www.fpga4fun.com/) - Some projects build on FPGA.\n- [32 Verilog Mini Projects](https://github.com/sudhamshu091/32-Verilog-Mini-Projects/) 📍![stars](https://img.shields.io/github/stars/sudhamshu091/32-Verilog-Mini-Projects) - 32 useful mini verilog projects for beginners.\n\n### Communication Technology\n\n- [ALEX FORENCICH](http://alexforencich.com/wiki/en/verilog/start) - Verilog IPs including PCIe/Ethernet/I2C/Uart etc.\n\n- [ALEX FORENCICH - AXI](https://github.com/alexforencich/verilog-axi) 📍![stars](https://img.shields.io/github/stars/alexforencich/verilog-axi) - Collection of AXI4 and AXI4 lite bus components. Most components are fully parametrizable in interface widths.\n- [TVIP - AXI](https://github.com/taichi-ishitani/tvip-axi) 📍![stars](https://img.shields.io/github/stars/taichi-ishitani/tvip-axi) - An UVM package of AMBA AXI4 VIP.\n- [PULP-platform - AXI](https://github.com/pulp-platform/axi) 📍![stars](https://img.shields.io/github/stars/pulp-platform/axi) - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication.\n- [ALEX FORENCICH - AXIS](https://github.com/alexforencich/verilog-axis) 📍![stars](https://img.shields.io/github/stars/alexforencich/verilog-axis) - Collection of AXI Stream bus components. Most components are fully parametrizable in interface widths.\n- [ALEX FORENCICH - IIC](https://github.com/alexforencich/verilog-i2c) 📍![stars](https://img.shields.io/github/stars/alexforencich/verilog-i2c) - I2C interface components. Includes full MyHDL testbench with intelligent bus cosimulation endpoints.\n- [corundum - NIC](https://github.com/corundum/corundum) 📍![stars](https://img.shields.io/github/stars/corundum/corundum)\n- [RIFFA - PCIe](https://github.com/KastnerRG/riffa) 📍![stars](https://img.shields.io/github/stars/KastnerRG/riffa) - Reusable Integration Framework for FPGA Acceleratorscommunication.\n- [ALEX FORENCICH - UART](http://github.com/alexforencich/verilog-uart/) 📍![stars](https://img.shields.io/github/stars/alexforencich/verilog-uart) - A basic UART to AXI Stream IP core, written in Verilog with cocotb testbenches.\n- [zipcpu - UART](https://github.com/ZipCPU/wbuart32) 📍![stars](https://img.shields.io/github/stars/ZipCPU/wbuart32) - A simple, basic, formally verified UART controller.\n- [C910 - UART](https://github.com/MeDove/openc910/tree/main/smart_run/logical) 📍\n\n### Information Technology\n\n#### RISC-V\n\n- [RISC-V Instruction Set Manual](https://github.com/riscv/riscv-isa-manual) - This repository contains the LaTeX source for the draft RISC-V Instruction Set Manual.\n\n- [RISC-V Exchange: Cores \u0026 SoCs](https://riscv.org/exchanges/cores-socs/) - A list of RICS-V cores and SoCs.\n- [PULP](https://github.com/pulp-platform/pulp) - Open source Parallel Ultra-Low-Power RISC-V core.\n- [openc910](https://github.com/T-head-Semi/openc910) 📍![stars](https://img.shields.io/github/stars/T-head-Semi/openc910) - OpenXuantie C910 Core.\n- [XiangShan](https://github.com/OpenXiangShan/XiangShan) 📍![stars](https://img.shields.io/github/stars/OpenXiangShan/XiangShan) - Open-source high-performance RISC-V processor.\n- [riscv-starship](https://github.com/riscv-zju/riscv-starship) 📍![stars](https://img.shields.io/github/stars/riscv-zju/riscv-starship) - Run rocket-chip on FPGA(Xilinx Virtex-7 VC707).\n- [Wujian100](https://github.com/T-head-Semi/wujian100_open) 📍![stars](https://img.shields.io/github/stars/T-head-Semi/wujian100_open) - A MCU base SoC.\n- [picorv32](https://github.com/YosysHQ/picorv32) 📍![stars](https://img.shields.io/github/stars/YosysHQ/picorv32) - A Size-Optimized RISC-V CPU.\n- [Hummingbirdv2 E203 Core and SoC](https://github.com/riscv-mcu/e203_hbirdv2) 📍![stars](https://img.shields.io/github/stars/riscv-mcu/e203_hbirdv2) [Docs](https://doc.nucleisys.com/hbirdv2/) - A Ultra-Low Power RISC-V Core.\n- [darkriscv](https://github.com/darklife/darkriscv) 📍![stars](https://img.shields.io/github/stars/darklife/darkriscv) - A proof of concept for the opensource RISC-V instruction set.\n- [CVA6 RISC-V CPU](https://github.com/openhwgroup/cva6) 📍![stars](https://img.shields.io/github/stars/openhwgroup/cva6) - An application class 6-stage RISC-V CPU capable of booting Linux.\n- [VexRiscv](https://github.com/SpinalHDL/VexRiscv) 📍![stars](https://img.shields.io/github/stars/SpinalHDL/VexRiscv) - A FPGA friendly 32 bit RISC-V CPU implementation.\n\n#### Others\n\n- [zipcpu](https://github.com/ZipCPU/zipcpu) ⭐📍![stars](https://img.shields.io/github/stars/ZipCPU/zipcpu) - with detailed comments.\n- [openmsp430](https://opencores.org/projects/openmsp430) - The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.\n- [Nyuzi Processor](https://github.com/jbush001/NyuziProcessor) 📍![stars](https://img.shields.io/github/stars/jbush001/NyuziProcessor) - GPGPU microprocessor architecture.\n\n## Tutorials and Courses 💬[Intro](./Tutorials%20and%20Courses/README.md)\n\n- [zipcpu](http://zipcpu.com/tutorial/) 👶 - Verilog, Formal Verification and Verilator Beginner's Tutorial\n- [WORLD OF ASIC](http://asic-world.com/) ⭐ - A great source of detailed VLSI tutorials and examples.\n\n### HDL\n\n- More information about hardware description language on [Awesome HDL](https://github.com/drom/awesome-hdl)\n\n#### Verilog Grammar\n\n- [Verilog TUTORIAL for beginners](http://www.referencedesigner.com/tutorials/verilog/verilog_01.php) 👶 - A tutorial based upon free Icarus Verilog compiler.\n- [ChipVerify: Verilog Tutorial](https://www.chipverify.com/verilog/verilog-tutorial) - A guide for someone new to Verilog.\n- [Verilog/SystemVerilog Guide](https://github.com/mikeroyal/Verilog-SystemVerilog-Guide) 📍![stars](https://img.shields.io/github/stars/mikeroyal/Verilog-SystemVerilog-Guide) - A guide covering Verilog \u0026 SystemVerilog.\n- [Verilog Tutorial - 菜鸟教程](https://www.runoob.com/w3cnote/verilog2-tutorial.html) 🚩 - Advanced tutorial for verilog.\n\n#### VHDL Grammar\n\n- [VHDL Guide](https://github.com/mikeroyal/VHDL-Guide) 📍![stars](https://img.shields.io/github/stars/mikeroyal/VHDL-Guide) - A guide covering VHDL.\n\n#### Chisel\n\n- [Learning Chisel and Scala Part I](https://vvviy.github.io/2018/12/01/Learning-Chisel-and-Scala-Part-I/) [Part II](https://vvviy.github.io/2018/12/12/Learning-Chisel-and-Scala-Part-II/) 🚩📍[Github](https://github.com/VVViy/VVViy.github.io)![stars](https://img.shields.io/github/stars/SpinalHDL/SpinalHDL) - A tutorial for chisel, no scala knowledge required.\n- [Chisel/FIRRTL](https://www.chisel-lang.org/) 💬[Doc](https://www.chisel-lang.org/chisel3/docs/introduction.html) 📍[Github](https://github.com/chipsalliance/chisel3)![stars](https://img.shields.io/github/stars/chipsalliance/chisel3) - Scala based HDL.\n\n#### SpinalHDL\n\n- [从 Verilog 到 SpinalHDL](https://blog.csdn.net/Pieces_thinking/article/details/118158954) 🚩 - A website navigation for SpinalHDL.\n- [SpinalHDL](https://spinalhdl.github.io/SpinalDoc-RTD/v1.6.0/SpinalHDL/Getting%20Started/getting_started.html) 📍[Github](https://github.com/SpinalHDL/SpinalHDL)![stars](https://img.shields.io/github/stars/SpinalHDL/SpinalHDL) - Scala based HDL.\n\n### Verification\n\n- [Verification Academy](https://verificationacademy.com/) - The most comprehensive resource for verification training.\n- [Verification Guide](https://www.verificationguide.com/p/home.html) - Tutorials with links to example codes on EDA Playground.\n- [Doulos](https://www.doulos.com) - Global training solutions for engineers creating the world's electronics products.\n- [testbench](http://www.testbench.in/) - Some training articals for systemverilog.\n- [ClueLogic](http://cluelogic.com) - Providing the clues to solve your verification problems.\n- [ChipVerify](https://www.chipverify.com/) - A simple and complete set of verilog/System Verilog/UVM tutorials.\n\n### Build a CPU\n\n- [RISC-V Guide](https://github.com/mikeroyal/RISC-V-Guide) 📍![stars](https://img.shields.io/github/stars/mikeroyal/RISC-V-Guide) - A guide covering the RISC-V Architecture.\n- [ARM Guide](https://github.com/mikeroyal/ARM-Guide) 📍![stars](https://img.shields.io/github/stars/mikeroyal/ARM-Guide) - A guide covering ARM architecture.\n- [nand2tetris](https://www.nand2tetris.org/) - Build an advanced computer from nand gate.\n- [Building a RISC-V CPU Core - edX](https://www.edx.org/course/building-a-risc-v-cpu-core) 📽 - Build a RISC-V cpu core. No prior knowledge of digital logic design is required.\n- [Build a Modern Computer from First Principles: From Nand to Tetris - coursera](https://www.coursera.org/learn/build-a-computer \"依据基本原理构建现代计算机：从与非门到俄罗斯方块（基于项目的课程）\") 📽 - Build a modern computer system.\n\n### FPGA\n\n- [FPGA Tutorial](https://github.com/LeiWang1999/FPGA) 🚩 📍![stars](https://img.shields.io/github/stars/LeiWang1999/FPGA) - Sharing excellent articles and projects related to FPGA.\n- [Complex Programmable Logic Device (CPLD) Guide](https://github.com/mikeroyal/CPLD-Guide) 📍![stars](https://img.shields.io/github/stars/mikeroyal/CPLD-Guide) - A guide covering CPLD.\n\n## Tools\n\n- [EDA Playground](https://www.edaplayground.com/) - Edit, save, simulate, synthesize SystemVerilog, Verilog, VHDL and other HDLs from your web browser.\n- [tree-core-ide](https://github.com/microdynamics-cpu/tree-core-ide)  📍![stars](https://img.shields.io/github/stars/microdynamics-cpu/tree-core-ide)- A VSCode-based HDL extension.\n- [WaveDrom](https://wavedrom.com/) - Digital Timing Diagram everywhere\n- [Icarus Verilog](http://iverilog.icarus.com/) 📍[Github](https://github.com/steveicarus/iverilog)![stars](https://img.shields.io/github/stars/steveicarus/iverilog) - A Verilog simulation and synthesis tool.\n- [GTKWave](http://gtkwave.sourceforge.net/) - GTKWave is a fully featured GTK+ based wave viewer.\n- [OpenROAD](https://theopenroadproject.org/) 💬[Doc](https://openroad.readthedocs.io/en/latest/main/README.html) 📍[Github](https://github.com/The-OpenROAD-Project/OpenROAD)![stars](https://img.shields.io/github/stars/The-OpenROAD-Project/OpenROAD) - An RTL-to-GDS Flow\n- More information about hardware dv tools on [Awesome Open Hardware Verification - Tools](https://github.com/ben-marshall/awesome-open-hardware-verification#Tools) and [Awesome HWD Tools](https://github.com/TM90/awesome-hwd-tools)\n\n## Forums\n\n- [EETOP](https://bbs.eetop.cn/) 🚩 - The most popular IC bbs in China.\n- [edaboard](https://www.edaboard.com/) - An EE World Online Resource.\n- [极术社区](https://aijishu.com/) 🚩 - A bbs sponsered by Arm China.\n\n## Online Judge Platforms\n\n- [HDL bits](https://hdlbits.01xz.net/wiki/Main_Page) - A collection of small circuit design exercises for practicing digital hardware design using Verilog Hardware Description Language (HDL).\n- [USTC Verilog OJ](https://verilogoj.ustc.edu.cn/oj) 🚩 - A verilog online judge service\n- [nowcoder - Verilog Part](https://www.nowcoder.com/exam/oj?page=1\u0026tab=Verilog%E7%AF%87\u0026topicId=301) - A verilog oj platform.\n\n## Games\n\n### PC\n\n- [MHRD](https://store.steampowered.com/app/576030/MHRD/) - Become a hardware engineer \u0026 Build your own CPU from NAND.\n\n### web\n\n- [NAND Game](https://nandgame.com/#) - Build a CPU from basic cells by dragging.\n\n### Mobile Phone\n\n- [与门](https://www.taptap.com/app/196676) 🚩 - Build an adder from nand.\n\n\u003e Discuss:\n\u003e QQ Group 830367636\n\u003e Email 673538982@qq.com\n","projects_url":"https://awesome.ecosyste.ms/api/v1/lists/qninth%2Fawesome-digital-ic/projects"}