{"id":13996085,"url":"https://github.com/1801BM1/vm80a","last_synced_at":"2025-07-22T23:31:14.622Z","repository":{"id":218677421,"uuid":"119828919","full_name":"1801BM1/vm80a","owner":"1801BM1","description":"i8080 precise replica in Verilog, based on reverse engineering of real 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Die photo\n\n![Die photo](/img/vm80a.jpg)\n\nLinks to raw photos (please, note, files are LARGE):\n- [Top metal, 11Kx10K, 95M](http://www.1801bm1.com/files/retro/580/images/580vm80a-2.jpg)\n- [Top metal, 11Kx10K, 140M](http://www.1801bm1.com/files/retro/580/images/580vm80a-3.jpg)\n- [Diffusion, 5.5Kx5K, 28M](http://www.1801bm1.com/files/retro/580/images/580vm80a-sil.jpg)\n\n## Abstract\nThe vm80a is the core built on the base of the revengineered real 580BM80A die.\nThe 580BM80A chip is the Soviet replica of early Intel i8080A microprocessor,\nand these ones are very close topologically.\n\nThe silicon techology parameters are:\n- 5 micron scale\n- one metal and one polycrystalline silicon layer\n- NMOS schematics with depletion mode loads\n- the extra high voltage source (+12V) is required\n- high voltage direct clock phases (+12V)\n- no built-in negative bias generator, extra negative voltage source is required\n\nThe reversing was performed in the following stages:\n- crystall decapsulation (with hot acid etching)\n- taking the panorama shapshot of combined upper metal and polysilicon layers\n- etching upper metal and polysilicon layers\n- taking the panorama shapshot of diffusion layer with the prints of polysilicon layer\n- vectorizing the photos in the SprintLayout editor\n- transferring the topology to the PCAD-2004 pcb editor\n- converting topology to PCAD-2004 schematics using the back annotation\n- writing the Verilog code on the precise schematics base\n- patching the code to eliminate the asynchronous nature of original circuits\n- simulating and testing the resulting vm80a core on the real FPGAs\n- thorough i8080 exerciser tests were passed successfully\n\n## Results\nThe project provides two i8080 models in Verilog - the one is pin-compatible with original\nprocessor and other is refactored to be implemented within SoC and has the Wishbone interface.\nBoth approaches are proven on the real boards and FPGAs.\nThe models are compact and fast enough, the typical speed and area for Wishbone-featured model\non the DE0 board (Cyclone EP3C16F484C6):\n- 104MHz clock, 607 LUTs and 187 flip-flops, no RAM blocks\n \n## Directory structure\n#### \\sch    \n- topology in Sprint Layout format\n- topology in PCD-2004 pcb format\n- schematics in PCD-2004 sch format\n- schematics in [pdf](/sch/vm80a.pdf) (gate level)\n\n#### \\org\n- synchronous vm80a core, all original timings are kept intact, \nincludes the wrapper for usage as in-place-substitution of real i8080/580BM80A \n          \n#### \\wbc\n- Wishbone compatible version of vm80a core, uses single clock, FPGA-optimized,\nfollows the original command execution timings\n\n#### \\tst\n- i8080 Exerciser test software and some other tests\n\n## Supported FPGA development boards:\n- [Altera DE0](http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English\u0026No=364)\n- [Altera DE1](http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English\u0026CategoryNo=53\u0026No=83)\n- [Altera DE2-115](http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English\u0026CategoryNo=139\u0026No=502)\n- [Alinx AX309](http://artofcircuits.com/product/alinx-ax309-spartan-6-fpga-development-board-xc6slx9-2ftg256c)\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2F1801BM1%2Fvm80a","html_url":"https://awesome.ecosyste.ms/projects/github.com%2F1801BM1%2Fvm80a","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2F1801BM1%2Fvm80a/lists"}