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基于 Xilinx FPGA 的药片装瓶系统\n\n\u003e 康京旸 - 322 - 2021210943\n\u003e\n\u003e https://github.com/3DRX/pill_loading\n\n\u003c!--toc:start--\u003e\n- [基于 Xilinx FPGA 的药片装瓶系统](#基于-xilinx-fpga-的药片装瓶系统)\n  - [开发环境](#开发环境)\n    - [流程](#流程)\n      - [仿真](#仿真)\n      - [编译](#编译)\n  - [设计内容](#设计内容)\n    - [功能概述](#功能概述)\n    - [结合开发板硬件资源的实现](#结合开发板硬件资源的实现)\n  - [实现细节](#实现细节)\n    - [编码风格](#编码风格)\n    - [代码结构](#代码结构)\n    - [模块划分](#模块划分)\n      - [工具类模块](#工具类模块)\n      - [驱动器](#驱动器)\n      - [逻辑控制器](#逻辑控制器)\n      - [主模块`main.vhd`](#主模块mainvhd)\n  - [总结](#总结)\n    - [遇到过的问题及解决方式](#遇到过的问题及解决方式)\n\u003c!--toc:end--\u003e\n\n## 开发环境\n\n- Ubuntu 22.04 LTS\n- Vivado v2022.2 (64-bit)\n- GHDL 1.0.0 (Ubuntu 1.0.0+dfsg-6) [Dunoon edition]\n- GTKWave\n- Minisys 开发板，搭载 Xilinx Artix-7（XC7A100T FGG484C-1）\n\n### 流程\n\n#### 仿真\n\n`./components/` 文件夹中以 `*_tb.vhd` 结尾的文件是测试文件，\n由于编译速度，平台兼容性等原因，测试通过开源工具 GHDL 与 GTKWave 进行。\n\n其中`./components/Makefile` 是运行测试的编译文件。\n将 Makefile 中 NAME 改为要测试的文件名，再修改相关编译指令参数，\n运行 `make` 即可生成 `wave.ghw` 文件。\n使用 GTKWave 打开 `wave.ghw`，即可看到模拟仿真波形。\n\n#### 编译\n\n常规的 Vivado 项目 Synthesis =\u003e Implementation =\u003e Generate Bit Stream 流程。\n\n对编译速度进行优化如下：\n- 在 Vivado 安装目录下 `./scripts/` 文件夹中添加 `Vivado_init.tcl` 文件，并写入：\n`set_param general.maxThreads 32` 即可使 Vivado 在编译时使用能利用的最多线程。\n- 将 `/` 目录下 `/swapfile` 文件扩容至 16G（与内存大小相同）。\n- 在 Vivado 项目设置中选择 Run Strategy 为 `Flow_RuntimeOptimized (Vivado Synthesis 2022)`\n和 `Flow_Quick (Vivado Implementation 2022)`，即为牺牲优化性能换取更快编译速度的策略。\n\n## 设计内容\n\n### 功能概述\n\n有两个模式，设置初始值模式与计数模式。\n\n在设置初始值模式下，接受键盘输入分别设定每瓶药片数和总瓶数。\n其中药片数最大值为 50，瓶数最大为 18。\n如果用户的输入超过了最大值，则按照最大值处理。\n\n在计数模式下，以 `0.5Hz` 的频率增加计数器，模拟药片的装入过程。\n当前累积装载药片超过设定的总数时，停止装载药片并播放提示音。\n\n有两个指示灯：红灯在设置初始值模式下亮，绿灯在计数模式下亮。\n\n### 结合开发板硬件资源的实现\n\n利用的开发板资源如下：\n- XC7A100T FGG484C-1 芯片\n- `100MHz` 晶振\n- 8 位数码管显示数字\n- 蜂鸣器\n- 方向键\n- 单刀双置开关\n- LED 灯\n- 数字矩阵键盘\n\n在设置初始值模式下，数码管的最右侧两位为每瓶药片数，次右侧两位为总瓶数。\n设置数值时，四位数中有一位会闪烁，标志着当前修改的位。\n开发板上有上、下、左、右、中共 5 个方向键，利用了其中左、中、右三个控制设置初始值模式。\n左右键选择当前修改的位，中键为确认按钮。\n\n开关用于切换模式，置0时设置初始值，置1时开始计数。\n计数时，数码管所有位均不闪烁。\n其中最右侧两位和次右侧两位分别表示当前瓶中药片数和已装满瓶数，左侧三位数表示总药片数。\n三组数之间用小数点分隔。\n\n## 实现细节\n\n### 编码风格\n\n使用 VHDL 语言，版本为 [VHDL 2008](https://docs.xilinx.com/r/en-US/ug901-vivado-synthesis/Supported-VHDL-2008-Features)。\n程序划分为不同模块（下文中的`entity`），主模块为`main.vhd`。每个`entity`分别写在单独的文件中，以`component`的形式被上层`entity`调用。\n\n### 代码结构\n\n- `main`\n    - `count_pill_controller`\n        - `pill_count_clk: divider`\n        - `buzz_controller`\n            - `buzz_clk: divider`\n        - `pill_counter`\n            - `sum_counter: counter`\n            - `pill: counter`\n            - `bottle: counter`\n    - `set_num_controller`\n        - `matrix_input`\n        - `bling_selecter`\n    - `BTN1: DeBounce`\n    - ...\n    - `BTN5: Debounce`\n    - `divide_bling: divider`\n    - `divide_debounce: divider`\n    - `divide_mos_refresh: divider`\n    - `ints_switcher`\n    - `mos_driver`\n    - `bling_driver`\n\n### 模块划分\n\n#### 工具类模块\n\n`divider.vhd` 分频器\n\n```vhdl\nentity divider is\n    port(\n            CLK: in std_logic; -- CLK: 原始时钟\n            RST: in std_logic; -- RST: 清零\n            N: in integer;     -- N: 源周期/输出周期（N=2时，2分频）\n            O: out std_logic   -- O: 输出时钟\n        );\nend entity divider;\n```\n\n`counter.vhd` 计数器\n```vhdl\nentity counter is\n    port(\n            CLK: in std_logic; -- CLK: 时钟\n            RST: in std_logic; -- RST: 清零\n            N: in integer;     -- N: 输入最大值\n            O: out integer;    -- O: 输出计数值 [0, N-1] 闭区间\n            C: out std_logic   -- C: 进位输出\n        );\nend entity counter;\n```\n\n`key_debounce.vhd` 按键消抖\n```vhdl\nentity DeBounce is\n    port(\n            Clock : in std_logic;     -- Clock: 时钟\n            Reset : in std_logic;     -- Reset: 清零\n            button_in : in std_logic; -- button_in: 输入原始信号\n            pulse_out : out std_logic -- pulse_out: 输出消抖后信号\n        );\nend DeBounce;\n```\n\n#### 驱动器\n\n`matrix_input.vhd` 矩阵键盘输入\n```vhdl\nentity matrix_input is\n    port(\n            CLK:in std_logic;                      -- CLK: 时钟\n            CLR:in std_logic;                      -- CKR: 清零\n            kcol:in std_logic_vector(3 downto 0);  -- kcol: 列信号\n            krow:out std_logic_vector(3 downto 0); -- krow: 行信号\n            seg_num:out integer                    -- seg_num: 输出数字\n        );\nend matrix_input;\n```\n\n`bling_driver.vhd` 数码管信号闪烁模块\n```vhdl\nentity bling_driver is\n    port (\n             bling_clk: in std_logic;                     -- 时钟\n             bling_bit: in std_logic_vector(7 downto 0);  -- 闪烁的位，1有效\n             MOS_INTS: in integer_vector(7 downto 0);     -- 数字原始信号\n             MOS_DOTS: in std_logic_vector(7 downto 0);   -- 小数点原始信号\n             O_MOS_INTS: out integer_vector(7 downto 0);  -- 数字输出信号\n             O_MOS_DOTS: out std_logic_vector(7 downto 0) -- 小数点输出信号\n         );\nend entity bling_driver;\n```\n\n`mos_driver.vhd` 数码管显示驱动\n```vhdl\nentity mos_driver is\n    port(\n            INTS: in integer_vector(7 downto 0);      -- 数字，为10清零\n            DOTS: in std_logic_vector(7 downto 0);    -- 小数点，'1' 不亮，'0' 亮\n            CLK: in std_logic;                        -- 时钟\n            OUTNUM: out std_logic_vector(7 downto 0); -- 输出数码管显示信号\n            SELNUM: out std_logic_vector(7 downto 0)  -- 输出数码管数位选择信号\n        );\nend mos_driver;\n```\n\n`buzz_controller.vhd` 蜂鸣器驱动\n```vhdl\nentity buzz_controller is\n    port (\n             CLK: in std_logic;      -- 100MHz 时钟\n             START: in std_logic;    -- 使能信号\n             BUZZ_OUT: out std_logic -- 输出到蜂鸣器的脉冲\n         );\nend entity buzz_controller;\n```\n\n#### 逻辑控制器\n\n`count_pill_controller.vhd` 药品计数模式控制器\n```vhdl\nentity count_pill_controller is\n    port (\n             CLK: in std_logic;                          -- 100MHz\n             START: in std_logic;                        -- 1有效\n             PILL_MAX: in integer;                       -- 每瓶最大药片数\n             BOTTLE_MAX: in integer;                     -- 最大瓶数\n             COUNT_INTS: out integer_vector(7 downto 0); -- 输出显示缓冲\n             BUZZ: out std_logic                         -- 输出蜂鸣器使能\n         );\nend entity count_pill_controller;\n```\n\n`set_num_controller.vhd` 设置最大值模式控制器\n```vhdl\nentity set_num_controller is\n    port (\n             CLK: in std_logic;                          -- 100MHz 时钟\n             START: in std_logic;                        -- 1 有效\n             S1: in std_logic;                           -- 右按钮\n             S2: in std_logic;                           -- 左按钮\n             S4: in std_logic;                           -- 确认按钮\n             kcol:in std_logic_vector(3 downto 0);       -- 矩阵键盘信号\n             krow:out std_logic_vector(3 downto 0);      -- 矩阵键盘信号\n             PILL_MAX: out integer;                      -- 每瓶最大药片数\n             BOTTLE_MAX: out integer;                    -- 最大瓶数\n             BLING_BIT: out std_logic_vector(7 downto 0); -- 正在闪烁的位\n             SET_INTS: out integer_vector(7 downto 0)    -- 输出显示缓冲\n         );\nend entity set_num_controller;\n```\n\n`ints_switcher.vhd` 两种模式下显示输出缓冲区切换模块\n```vhdl\nentity ints_switcher is\n    port (\n             START: in std_logic;                       -- 标志着在哪个模式\n             COUNT_INTS: in integer_vector(7 downto 0); -- 计数模式输出缓冲\n             SET_INTS: in integer_vector(7 downto 0);   -- 置数模式输出缓冲\n             MOS_INTS: out integer_vector(7 downto 0)   -- 选择当前模式的输出\n         );\nend entity ints_switcher;\n```\n\n#### 主模块`main.vhd`\n\n\u003e 控制红、绿指示灯的逻辑直接写在了主模块中\n\n输入输出端口\n```vhdl\nentity main is\n    port(\n            CLK: in std_logic;\n            START: in std_logic;\n            kcol:in std_logic_vector(3 downto 0);\n            krow:out std_logic_vector(3 downto 0);\n            S1: in std_logic;\n            S2: in std_logic;\n            S3: in std_logic;\n            S4: in std_logic;\n            S5: in std_logic;\n            OUTNUM: out std_logic_vector(7 downto 0);\n            SELNUM: out std_logic_vector(7 downto 0);\n            RED: out std_logic;\n            GREEN: out std_logic;\n            BUZZ: out std_logic\n        );\nend entity main;\n```\n\n`signal` 存储模块间的状态量\n```vhdl\n-- 消抖后的按钮\nsignal OS1: std_logic;\nsignal OS2: std_logic;\nsignal OS3: std_logic;\nsignal OS4: std_logic;\nsignal OS5: std_logic;\n-- 分频后的时钟\nsignal one_second: std_logic := '0';\nsignal mos_refresh_clk: std_logic := '0';\nsignal bling_clk: std_logic := '0';\nsignal debounce_clk: std_logic := '0';\n-- 数码管显示输出\n-- 计数值\nsignal count_ints: integer_vector(7 downto 0) := (others =\u003e 0);\n-- 设置值\nsignal set_ints: integer_vector(7 downto 0) := (others =\u003e 0);\n-- 显示输出值\nsignal mos_ints: integer_vector(7 downto 0) := (others =\u003e 0);\nsignal mos_dots: std_logic_vector(7 downto 0) := \"11101011\";\n-- 加闪烁后的输出值\nsignal o_mos_ints: integer_vector(7 downto 0) := (others =\u003e 0);\nsignal o_mos_dots: std_logic_vector(7 downto 0) := (others =\u003e '0');\n-- 正在闪烁的位，1有效\nsignal bling_bit: std_logic_vector(7 downto 0);\n-- 键盘输入的数字\nsignal matrix_num: integer := 0;\n-- 当前设定的最大值\nsignal t_pill_max: integer;\nsignal t_bottle_max: integer;\n-- 红灯状态\nsignal red_light: std_logic;\n-- 绿灯状态\nsignal green_light: std_logic;\n```\n\n---\n\n各模块逻辑实现细节见[源码](https://github.com/3DRX/pill_loading)\n\n## 总结\n\n在使用硬件描述语言设计较为复杂的系统时，我发现了硬件与软件在编程中的许多相同点与不同点。\n- 相同点\n    1. 在进行设计时，都要遵循自定向下的设计方式，将复杂功能拆分为多个简单功能的组合。\n    2. 将模块拆分到不同文件中，组成软件包，也调用库中的软件包，便于复用。\n    3. 同一语言的不同版本之间区别不可忽略，语法不一定向后兼容，在进行开发时要对环境充分了解，避免因语言、环境版本导致的问题。\n    4. 在接触新环境时，都需要大量阅读文档。\n- 不同点\n    1. 硬件设计的逻辑更多的是并行的而非软件开发中所习惯的串行的。\n    2. 硬件开发需要对于硬件本身十分了解。\n    3. 硬件开发过程中模拟仿真十分重要，进行模拟仿真看似增长了开发流程，却反而能使问题更早被发现，提高开发效率。\n\n### 遇到过的问题及解决方式\n\n1. 模拟仿真与实际片上跑起来的行为不一致，原因可能是在同一个 process 中 if - else 的层数过多，\n导致信号在最终生成的硬件中会有比较大的延迟。解决方式：尽量避免过多的 if - else 嵌套，在需要两个分支\n完全并行的地方使用 case - when 语句。\n\n2. 教程中的“硬件手册”上的信息与实际硬件的情况不一致。解决方式：查阅硬件厂商的文档，锻炼查阅文档以及英语阅读能力。\n\n3. 对多个连续串行的 `\u003c=` 赋值语句在 VHDL 底层实现方式不了解，导致写出行为不符合预期的代码。\n解决方式：查阅书籍与文档资料，深入学习相关内容。\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2F3drx%2Fpill_loading","html_url":"https://awesome.ecosyste.ms/projects/github.com%2F3drx%2Fpill_loading","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2F3drx%2Fpill_loading/lists"}