{"id":13777208,"url":"https://github.com/AUCOHL/DFFRAM","last_synced_at":"2025-05-11T11:33:04.339Z","repository":{"id":38094335,"uuid":"311306901","full_name":"AUCOHL/DFFRAM","owner":"AUCOHL","description":"Standard Cell Library based Memory Compiler using FF/Latch cells","archived":false,"fork":false,"pushed_at":"2024-04-29T08:48:34.000Z","size":49236,"stargazers_count":123,"open_issues_count":30,"forks_count":33,"subscribers_count":14,"default_branch":"main","last_synced_at":"2024-05-18T21:36:38.169Z","etag":null,"topics":["asic-design","electronics-design","verilog","vlsi","vlsi-circuits","vlsi-physical-design"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/AUCOHL.png","metadata":{"files":{"readme":"Readme.md","changelog":null,"contributing":"Contributing.md","funding":null,"license":"License","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":"Authors","dei":null,"publiccode":null,"codemeta":null}},"created_at":"2020-11-09T10:46:47.000Z","updated_at":"2024-08-03T18:10:47.894Z","dependencies_parsed_at":"2024-01-07T17:10:01.558Z","dependency_job_id":"d2b73735-6f43-4a32-84c7-4579ec39cbda","html_url":"https://github.com/AUCOHL/DFFRAM","commit_stats":null,"previous_names":[],"tags_count":7,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/AUCOHL%2FDFFRAM","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/AUCOHL%2FDFFRAM/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/AUCOHL%2FDFFRAM/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/AUCOHL%2FDFFRAM/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/AUCOHL","download_url":"https://codeload.github.com/AUCOHL/DFFRAM/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":225043067,"owners_count":17411924,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["asic-design","electronics-design","verilog","vlsi","vlsi-circuits","vlsi-physical-design"],"created_at":"2024-08-03T18:00:39.460Z","updated_at":"2024-11-17T13:30:34.075Z","avatar_url":"https://github.com/AUCOHL.png","language":"Verilog","funding_links":[],"categories":["Generators","Verilog"],"sub_categories":[],"readme":"\u003ch1 align=\"center\"\u003e DFFRAM Compiler\u003c/h1\u003e\n\u003cp align=\"center\"\u003e\n  \u003ca href=\"https://colab.research.google.com/github/Cloud-V/DFFRAM/blob/main/dffram.ipynb\"\u003e\u003cimg src=\"https://colab.research.google.com/assets/colab-badge.svg\" alt=\"Open in Google Colab\"/\u003e\u003c/a\u003e\n\u003c/p\u003e\n\u003cp align=\"center\"\u003e\n    \u003ca href=\"https://opensource.org/licenses/Apache-2.0\"\u003e\u003cimg src=\"https://img.shields.io/badge/License-Apache%202.0-blue.svg\" alt=\"License: Apache 2.0\"/\u003e\u003c/a\u003e\n    \u003cimg src=\"https://github.com/Cloud-V/DFFRAM/actions/workflows/main.yml/badge.svg?branch=main\" alt=\"CI Status\" /\u003e\n    \u003ca href=\"https://invite.skywater.tools\"\u003e\u003cimg src=\"https://img.shields.io/badge/Community-Skywater%20PDK%20Slack-ff69b4?logo=slack\" alt=\"Invite to the Skywater PDK Slack\"/\u003e\u003c/a\u003e\n    \u003ca href=\"https://github.com/psf/black\"\u003e\u003cimg src=\"https://img.shields.io/badge/code%20style-black-000000.svg\" alt=\"Code Style: Black\"/\u003e\u003c/a\u003e\n\u003c/p\u003e\n\nStandard Cell Library based Memory Compiler using DFF/Latch cells.\n\n# ✨ Installation \u0026 Usage\n\nSee [this document](./docs/Usage.md).\n\nYou can try the\n[Google Colaboratory](https://colab.research.google.com/github/Cloud-V/DFFRAM/blob/main/dffram.ipynb),\nbut it is a bit out-of-date at this point.\n\n## Platform Support Status\n\n| Configured Platform | Working | Silicon-proven\\* |\n| - | - | - |\n| `sky130A` | Yes | Yes |\n| `sky130B` | Yes | No |\n| `gf180mcuD` | No\\* (Hold violations in the Netlist) | No |\n\n\u003e \\* Silicon proven does not imply that you should use it without whole-system,\n\u003e timing-annotated simulation to make sure that it works for your circuit.\n\u003e\n\u003e There may be design-specific complications that may render DFFRAM (and indeed\n\u003e the entire chip) unusable. Proceed with caution.\n\n# Overview\n\nThe objective of this project is to develop a DFF/Latch-based RAM, Register File\nand Cache custom compilation flow that utilizes standard cell libraries\nfollowing a standard ASIC (Application Specific Integrated Circuit)\nimplementation approach. Different views (HDL netlist, HDL functional models,\nLEF, GDS, Timing, …) are all generated for a given size configuration.\n\nThe layout targets highly compact designs (85%+) as the cells are placed on the\nfloor plan using a custom placer. Moreover, the custom placer ensures that the\nrouting will be relatively simple. Currently, the compiler uses OpenROAD routers\nto route the macros with great success.\n\nThe Compiler relies on basic building blocks to construct the layout of\ndifferent RAM/RF/Cache configurations. Check\n[the compiler documentation](./docs/) for more info. The following shows how a\n32x32 memory (DFF based) is constructed.\n\n![](./docs/img/ram_ex.png)\n\nThe generated layouts by the DFFRAM compilers for RAM32 as well as its building\nblocks are as follows:\n\n* First, a byte, which is just 8 bits placed together...\n  ![GDS layout of a byte](./docs/img/1x8.png)\n\n* Put four of those side by side, and you get a 32-bit word...\n  ![GDS layout of a word](./docs/img/1x32.png)\n\n* Stack eight of those for an 8 word bank of RAM...\n  ![GDS layout of 8 words stacked vertically](./docs/img/8x32.png)\n\n* And stack 4 of these 8 words for a kilobit of RAM!\n  ![GDS layout of 4x8 words stacked vertically](./docs/img/32x32.png)\n\n* We can keep going, but these images aren't getting any smaller. As a bonus\n  though, here is 64 kilobits: ![8kbytes](./docs/img/8kb_layout.png)\n\n\u003e That stuff you see on the right of each image? It's clock gates, decoders and\n\u003e the like. Don't worry about it.\n\nCurrently, the can compiler generate the layout of the following configurations:\n\n\u003e 1RW1R variants are temporarily disabled due to a bug.\n\n* RAM\n  * 32 words with byte write enable (1RW and 1RW1R).\n  * 128 words with byte write enable (1RW and 1RW1R).\n  * 256 words with byte write enable (1RW and 1RW1R).\n  * 512 words with byte write enable (1RW and 1RW1R).\n  * 1024 words with byte write enable (1RW and 1RW1R).\n  * 2048 words with byte write enable (1RW and 1RW1R).\n* Register File\n  * 32 x 32-bit words (2R1W)\n\nThe [`OpenLane/`](./OpenLane) folder will contain good known OpenLane\nconfigurations to build DFFRAM different macros.\n\n## File Structure\n\n* `.github` contains files for GitHub actions.\n* `docs/` contains documentation (😮)\n* `rtl/` contains RTL RAM file generators for benchmarking and comparison\n  purposes.\n* `platforms/` contains PDK-specific files:\n  * `\u003cpdk-name\u003e/`\n    * `\u003cscl-name\u003e/`\n      * `_building_blocks/` contains a hierarchy of building blocks supported by\n        the compiler.\n* `placeram/` is the custom placer Python module.\n* `scripts/` has assisting scripts used by the flow.\n* `dffram.py` is the compilation flow going from building blocks to LVS.\n\n# Comparisons\n\nThe following table compares the areas and bit densities of RAM macros generated\nusing different means.\n\n\u003ctable\u003e\n  \u003ctr\u003e\n    \u003cth rowspan=\"2\"\u003eSize\u003csup\u003e1\u003c/sup\u003e\u003c/th\u003e \n    \u003cth colspan=\"2\"\u003eOpenRAM\u003csup\u003e2\u003c/sup\u003e\u003c/th\u003e \n    \u003cth colspan=\"2\"\u003eDFFRAM Compiler\u003c/th\u003e \n    \u003cth colspan=\"2\"\u003eDFFRAM/OpenLane\u003c/th\u003e \n    \u003cth colspan=\"2\"\u003eRTL/OpenLane\u003c/th\u003e\n  \u003c/tr\u003e\n  \u003ctr style=\"border-top:4px solid darkblue;\"\u003e\n    \u003ctd\u003e Dim WxH (μm) \u003c/td\u003e \u003ctd\u003e Bit Density (bits/mm\u003csup\u003e2\u003c/sup\u003e) \u003c/td\u003e\n    \u003ctd\u003e Dim WxH (μm) \u003c/td\u003e \u003ctd\u003e Bit Density (bits/mm\u003csup\u003e2\u003c/sup\u003e) \u003c/td\u003e\n    \u003ctd\u003e Dim WxH (μm) \u003c/td\u003e \u003ctd\u003e Bit Density (bits/mm\u003csup\u003e2\u003c/sup\u003e) \u003c/td\u003e\n    \u003ctd\u003e Dim WxH (μm) \u003c/td\u003e \u003ctd\u003e Bit Density (bits/mm\u003csup\u003e2\u003c/sup\u003e) \u003c/td\u003e\n  \u003c/tr\u003e\n  \u003ctr\u003e\n    \u003ctd\u003e 512 bytes \u003c/td\u003e\n    \u003ctd\u003e N/A \u003c/td\u003e \u003ctd\u003e N/A \u003c/td\u003e\n    \u003ctd\u003e 396.52 x 388.96 \u003c/td\u003e \u003ctd\u003e 26,557 \u003c/td\u003e\n    \u003ctd\u003e 527.46 x 527.46 \u003c/td\u003e \u003ctd\u003e 14,722 \u003c/td\u003e\n    \u003ctd\u003e 680.25 x 690.97 \u003c/td\u003e \u003ctd\u003e 8,714 \u003c/td\u003e\n  \u003c/tr\u003e\n  \u003ctr\u003e\n    \u003ctd\u003e 1 kbytes \u003c/td\u003e\n    \u003ctd\u003e 386 x 456 \u003c/td\u003e \u003ctd\u003e 46,541 \u003c/td\u003e\n    \u003ctd\u003e 792.58  x 397.12 \u003ctd\u003e 26,027 \u003c/td\u003e\n    \u003ctd\u003e 975.01 x 985.73 \u003c/td\u003e \u003ctd\u003e 8,523 \u003c/td\u003e\n    \u003ctd\u003e 1,050 x 1,060 \u003c/td\u003e \u003ctd\u003e 7,360 \u003c/td\u003e\n  \u003c/tr\u003e\n  \u003ctr\u003e\n    \u003ctd\u003e 2 kbytes \u003c/td\u003e\n    \u003ctd\u003e 659.98 x 398.18  \u003c/td\u003e \u003ctd\u003e 62,372 \u003c/td\u003e\n    \u003ctd\u003e 792.58 x 786.08 \u003c/td\u003e \u003ctd\u003e 26,297 \u003c/td\u003e\n    \u003ctd\u003e 1374.46 x 1385.18 \u003c/td\u003e \u003ctd\u003e 8,605 \u003c/td\u003e\n    \u003ctd\u003e 1,439.615 x 1,450.335 \u003c/td\u003e \u003ctd\u003e 7,847 \u003c/td\u003e\n  \u003c/tr\u003e\n  \u003ctr\u003e\n    \u003ctd\u003e 4 kbytes \u003c/td\u003e\n    \u003ctd\u003e 670.86 x 651.14 \u003c/td\u003e \u003ctd\u003e 75,014 \u003c/td\u003e\n    \u003ctd\u003e 1,584.24 x 788.8 \u003c/td\u003e \u003ctd\u003e 26,196 \u003c/td\u003e\n    \u003ctd\u003e 1940.45 x 1951.17 \u003c/td\u003e \u003ctd\u003e 8,654 \u003c/td\u003e\n    \u003ctd\u003e 2,074 x 2,085 \u003c/td\u003e \u003ctd\u003e 7,578 \u003c/td\u003e\n\n\u003c/tr\u003e\n  \u003ctr\u003e\n    \u003ctd\u003e 8 kbytes \u003c/td\u003e\n    \u003ctd\u003e N/A \u003c/td\u003e \u003ctd\u003e N/A \u003c/td\u003e\n    \u003ctd\u003e 1,589 x 1,572\u003c/td\u003e \u003ctd\u003e 26,229 \u003c/td\u003e\n    \u003ctd\u003e TBD \u003c/td\u003e \u003ctd\u003e TBD \u003c/td\u003e\n    \u003ctd\u003e 2,686.610 x 2,697.330 \u003c/td\u003e \u003ctd\u003e 9,043 \u003c/td\u003e\n  \u003c/tr\u003e\n\u003c/table\u003e\n\n\u003csup\u003e1\u003c/sup\u003e All support 32-bit word reads and 1, 2, and 4 bytes\nwrites.\\\n\u003csup\u003e2\u003c/sup\u003e Values are based on the original layout produced by the\ncompiler. OpenRAM macros are typically wrapped to be useful w/ automated PnR\nASIC flows.\n\n# ⚖️ Copyright and Licensing\n\n\u003ca id=\"copyright-and-licensing\"\u003e\u003c/a\u003e\n\nCopyright ©2020-2023 The American University in Cairo\n\nLicensed under the Apache License, Version 2.0 (the \"Open Source License\"); you\nmay not use this file except in compliance with the Open Source License. You may\nobtain a copy of the Open Source License at the root of this repository (see the\nfile 'License') or at\n\n\u003e http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software distributed\nunder the Open Source License is distributed on an \"AS IS\" BASIS, WITHOUT\nWARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the Open\nSource License for the specific language governing permissions and limitations\nunder the Open Source License.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FAUCOHL%2FDFFRAM","html_url":"https://awesome.ecosyste.ms/projects/github.com%2FAUCOHL%2FDFFRAM","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FAUCOHL%2FDFFRAM/lists"}