{"id":13649092,"url":"https://github.com/AUCOHL/Fault","last_synced_at":"2025-04-22T12:33:27.429Z","repository":{"id":38024646,"uuid":"190896335","full_name":"AUCOHL/Fault","owner":"AUCOHL","description":"A complete open-source design-for-testing (DFT) Solution","archived":false,"fork":false,"pushed_at":"2024-11-01T17:18:05.000Z","size":4485,"stargazers_count":135,"open_issues_count":9,"forks_count":30,"subscribers_count":11,"default_branch":"main","last_synced_at":"2024-11-01T18:23:23.129Z","etag":null,"topics":["atpg","dft","eda","fault-simulation","jtag","scan-chains","stuck-at","testing","verilog","verilog-hdl","vlsi-cad"],"latest_commit_sha":null,"homepage":"","language":"Swift","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/AUCOHL.png","metadata":{"files":{"readme":"Readme.md","changelog":null,"contributing":"Contributing.md","funding":null,"license":"License","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2019-06-08T14:18:53.000Z","updated_at":"2024-11-01T17:18:09.000Z","dependencies_parsed_at":"2024-06-16T17:24:16.794Z","dependency_job_id":"bb42dc3d-5162-498e-915e-27c193b36291","html_url":"https://github.com/AUCOHL/Fault","commit_stats":null,"previous_names":[],"tags_count":22,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/AUCOHL%2FFault","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/AUCOHL%2FFault/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/AUCOHL%2FFault/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/AUCOHL%2FFault/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/AUCOHL","download_url":"https://codeload.github.com/AUCOHL/Fault/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":223896472,"owners_count":17221441,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["atpg","dft","eda","fault-simulation","jtag","scan-chains","stuck-at","testing","verilog","verilog-hdl","vlsi-cad"],"created_at":"2024-08-02T01:04:45.990Z","updated_at":"2024-11-09T23:30:55.334Z","avatar_url":"https://github.com/AUCOHL.png","language":"Swift","funding_links":[],"categories":["Swift","Circuit Compilers"],"sub_categories":[],"readme":"\u003ch1 align=\"center\"\u003e🧪 Fault\u003c/h1\u003e\n\n\u003cp align=\"center\"\u003e\n  \u003ca href=\"https://developer.apple.com/swift/\"\u003e\u003cimg src=\"https://img.shields.io/badge/Swift-5.8-orange?logo=swift\" alt=\"Swift 5.8 or higher\"/\u003e\u003c/a\u003e\n  \u003ca href=\"https://fault.readthedocs.io/en/latest/\"\u003e\u003cimg src=\"https://readthedocs.org/projects/fault/badge\" alt=\"Read the Docs\"/\u003e\u003c/a\u003e\n  \u003ca href=\"https://nixos.org/\"\u003e\u003cimg src=\"https://img.shields.io/static/v1?logo=nixos\u0026logoColor=white\u0026label=\u0026message=Built%20with%20Nix\u0026color=41439a\"   \n alt=\"Built with Nix\"/\u003e\u003c/a\u003e\n\u003c/p\u003e   \n\n\nFault is a complete open source design for testing (DFT) Solution that includes automatic test pattern generation for netlists, scan chain stitching, synthesis scripts and a number of other convenience features.\n\n![A flowchart demonstrating the Fault flow](./docs/flow.png)\n\n# Installation and Usage\nSee the documentation at https://fault.readthedocs.io.\n\n# Copyright \u0026 Licensing\nAll rights reserved ©2018-2024 The American University in Cairo and other contributors. Fault is available under the Apache 2.0 License: See `License`.\n\nSOFTWARE INCLUDED WITH SOME FAULT DISTRIBUTIONS, I.E. ATALANTA AND PODEM, WHILE\nFREE TO DISTRIBUTE, ARE PROPRIETARY, AND MAY NOT BE USED FOR COMMERCIAL\nPURPOSES.\n\n# References\n- Z. Navabi, Digital System Test and Testable Design : Using Hdl Models and\n  Architectures. 2010;2011;. DOI: 10.1007/978-1-4419-7548-5.\n  [Book](https://ieeexplore.ieee.org/book/5266057)\n- Shinya Takamaeda-Yamazaki: Pyverilog: A Python-based Hardware Design\n  Processing Toolkit for Verilog HDL, 11th International Symposium on Applied\n  Reconfigurable Computing (ARC 2015) (Poster), Lecture Notes in Computer\n  Science, Vol.9040/2015, pp.451-460, April 2015.\n  [Paper](http://link.springer.com/chapter/10.1007/978-3-319-16214-0_42)\n\n# Publication(s)\n- M. Abdelatty, M. Gaber, M. Shalan, \"Fault: Open Source EDA’s Missing DFT\n  Toolchain,\" IEEE Design \u0026 Test Magazine. April 2021.\n  [Paper](https://ieeexplore.ieee.org/document/9324799)\n- Mohamed Gaber, Manar Abdelatty, and Mohamed Shalan, \"Fault, an Open Source DFT\n  Toolchain,\" Article No.13, Workshop on Open-Source EDA Technology (WOSET),\n  2019. [Paper](https://woset-workshop.github.io/PDFs/2019/a13.pdf)\n\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FAUCOHL%2FFault","html_url":"https://awesome.ecosyste.ms/projects/github.com%2FAUCOHL%2FFault","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FAUCOHL%2FFault/lists"}