{"id":13772957,"url":"https://github.com/DFiantHDL/DFHDL","last_synced_at":"2025-05-11T05:34:02.416Z","repository":{"id":41522435,"uuid":"192230005","full_name":"DFiantHDL/DFHDL","owner":"DFiantHDL","description":"DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language","archived":false,"fork":false,"pushed_at":"2024-11-15T16:37:57.000Z","size":51874,"stargazers_count":80,"open_issues_count":4,"forks_count":9,"subscribers_count":7,"default_branch":"main","last_synced_at":"2024-11-15T17:34:17.485Z","etag":null,"topics":["asic","dataflow","dataflow-programming","fpga","hdl"],"latest_commit_sha":null,"homepage":"https://dfianthdl.github.io/","language":"Scala","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"lgpl-3.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/DFiantHDL.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"COPYING.LESSER","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2019-06-16T19:42:03.000Z","updated_at":"2024-11-15T16:38:01.000Z","dependencies_parsed_at":"2023-10-01T12:32:13.954Z","dependency_job_id":"1bcee837-4e0c-4091-ba45-d5365dcd1969","html_url":"https://github.com/DFiantHDL/DFHDL","commit_stats":null,"previous_names":["dfianthdl/dfiant"],"tags_count":45,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/DFiantHDL%2FDFHDL","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/DFiantHDL%2FDFHDL/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/DFiantHDL%2FDFHDL/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/DFiantHDL%2FDFHDL/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/DFiantHDL","download_url":"https://codeload.github.com/DFiantHDL/DFHDL/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":225017631,"owners_count":17407807,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["asic","dataflow","dataflow-programming","fpga","hdl"],"created_at":"2024-08-03T17:01:09.611Z","updated_at":"2024-11-17T08:30:35.992Z","avatar_url":"https://github.com/DFiantHDL.png","language":"Scala","readme":"# DFiant HDL\n---\n![Build Status](https://github.com/DFiantHDL/DFiant/workflows/Build/badge.svg)\n[![dfhdl Scala version support](https://index.scala-lang.org/dfianthdl/dfhdl/dfhdl/latest.svg)](https://index.scala-lang.org/dfianthdl/dfhdl/dfhdl)\n[![Discord Chat](https://img.shields.io/discord/721461308297576598.svg)](https://discord.gg/) \n[![Scala Steward badge](https://img.shields.io/badge/Scala_Steward-helping-blue.svg?style=flat\u0026logo=data:image/png;base64,iVBORw0KGgoAAAANSUhEUgAAAA4AAAAQCAMAAAARSr4IAAAAVFBMVEUAAACHjojlOy5NWlrKzcYRKjGFjIbp293YycuLa3pYY2LSqql4f3pCUFTgSjNodYRmcXUsPD/NTTbjRS+2jomhgnzNc223cGvZS0HaSD0XLjbaSjElhIr+AAAAAXRSTlMAQObYZgAAAHlJREFUCNdNyosOwyAIhWHAQS1Vt7a77/3fcxxdmv0xwmckutAR1nkm4ggbyEcg/wWmlGLDAA3oL50xi6fk5ffZ3E2E3QfZDCcCN2YtbEWZt+Drc6u6rlqv7Uk0LdKqqr5rk2UCRXOk0vmQKGfc94nOJyQjouF9H/wCc9gECEYfONoAAAAASUVORK5CYII=)](https://scala-steward.org)\n\nWelcome to the DFiant hardware description language (DFHDL) repository! \n\nDFHDL is a dataflow HDL and is embedded as a library in the [Scala programming language](https://www.scala-lang.org/). DFiant enables timing-agnostic and device-agnostic hardware description by using dataflow firing rules as logical constructs, coupled with modern software language features (e.g., inheritance, polymorphism, pattern matching) and classic HDL features (e.g., bit-accuracy, input/output ports). Additionally, DFHDL integrates two additional levels of hardware description abstractions: register-transfer (RT), which is equivalent to languages like Chisel and Amaranth; and event-driven (ED), which is equivalent to Verilog and VHDL. \n\nRead the documentation: https://dfianthdl.github.io/\n\n\n## Acknowledgement\n\nPrevious version of this work (simply called \"DFiant\" at the time) has been supported by EU H2020 ICT project LEGaTO, contract #780681.\n","funding_links":[],"categories":["Circuit Compilers"],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FDFiantHDL%2FDFHDL","html_url":"https://awesome.ecosyste.ms/projects/github.com%2FDFiantHDL%2FDFHDL","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FDFiantHDL%2FDFHDL/lists"}