{"id":13646068,"url":"https://github.com/FPGA-Systems/drawio-hdl-builder","last_synced_at":"2025-04-21T17:31:56.718Z","repository":{"id":134712946,"uuid":"605724640","full_name":"FPGA-Systems/drawio-hdl-builder","owner":"FPGA-Systems","description":"Drawio =\u003e VHDL and Verilog","archived":false,"fork":false,"pushed_at":"2023-10-15T23:17:19.000Z","size":2026,"stargazers_count":51,"open_issues_count":0,"forks_count":9,"subscribers_count":6,"default_branch":"main","last_synced_at":"2024-11-09T19:41:21.066Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"CSS","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/FPGA-Systems.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2023-02-23T19:11:13.000Z","updated_at":"2024-09-14T09:34:18.000Z","dependencies_parsed_at":"2023-10-16T14:05:56.450Z","dependency_job_id":"a4cab507-2421-4eed-9642-1503304809be","html_url":"https://github.com/FPGA-Systems/drawio-hdl-builder","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/FPGA-Systems%2Fdrawio-hdl-builder","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/FPGA-Systems%2Fdrawio-hdl-builder/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/FPGA-Systems%2Fdrawio-hdl-builder/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/FPGA-Systems%2Fdrawio-hdl-builder/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/FPGA-Systems","download_url":"https://codeload.github.com/FPGA-Systems/drawio-hdl-builder/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":250100566,"owners_count":21374967,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-02T01:02:47.824Z","updated_at":"2025-04-21T17:31:55.217Z","avatar_url":"https://github.com/FPGA-Systems.png","language":"CSS","funding_links":[],"categories":["CSS"],"sub_categories":[],"readme":"# Drawio HDL Builder\n\nThis tool provide an ability to generate wrappers according project hierarchy created in [Drawio](https://www.diagrams.net/) tool.\n\nDrawio HDL Builder is not a part of Drawio extensions, it's a separate web-based page, running locally on your PC (simple HTML page, working with any web browser)\n\nWe provide a small library FSLib which will help you build project hierarchy with instances, connecting and then generate HDL (VHDL and Verilog) code.\n\n![](/img/0.png)\n\n## How to start\n0. Download and unzip this \"Drawio HDL Builder\" repository  \n1. Download and install [Drawio](https://www.diagrams.net/) or use [web-version](https://app.diagrams.net/)\n\n2. Create a new diagram in Drawio\n3. Remove \"Compressed\" checkbox in diagram settings: File =\u003e Properties =\u003e uncheck \"Compressed\" =\u003e Apply\n![](/img/2.jpg)\n4. Assign FSLib : File =\u003e Open Library\\\n![](/img/1.jpg) \n5. Use prepared template from FSLib to create project hierarchy. Learn more from [this tutorial](/docs/step_0.md)\n6. After you complete open **index.html** file from downloaded  \"Drawio HDL Builder\" repository\n![](/img/3.png)\n7. Choose your .drawio diagram file\n8. Press \"Do Magic\" button\n9. Select necessary modules from project using checkboxes, \"Select All\" or \"Clear All\" buttons\n10. Press \"Download\" button to save files. Press allow to multiple downloads, if your browser ask. \n\n\n\nPS: do not look at source code, except StackOverflow it's terrible.\n\n\n\n\n\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FFPGA-Systems%2Fdrawio-hdl-builder","html_url":"https://awesome.ecosyste.ms/projects/github.com%2FFPGA-Systems%2Fdrawio-hdl-builder","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FFPGA-Systems%2Fdrawio-hdl-builder/lists"}