{"id":13427762,"url":"https://github.com/Featherweight-IP/fwrisc","last_synced_at":"2025-03-16T00:32:16.921Z","repository":{"id":45623871,"uuid":"155328026","full_name":"Featherweight-IP/fwrisc","owner":"Featherweight-IP","description":"Featherweight RISC-V implementation","archived":false,"fork":false,"pushed_at":"2022-01-17T17:23:23.000Z","size":3096,"stargazers_count":52,"open_issues_count":2,"forks_count":9,"subscribers_count":6,"default_branch":"master","last_synced_at":"2024-10-28T07:45:07.694Z","etag":null,"topics":["risc-v","verilog","zephyr"],"latest_commit_sha":null,"homepage":null,"language":"SystemVerilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/Featherweight-IP.png","metadata":{"files":{"readme":"README.md","changelog":"ChangeLog.txt","contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2018-10-30T05:13:10.000Z","updated_at":"2024-04-17T22:59:46.000Z","dependencies_parsed_at":"2022-09-22T08:30:47.131Z","dependency_job_id":null,"html_url":"https://github.com/Featherweight-IP/fwrisc","commit_stats":null,"previous_names":[],"tags_count":1,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Featherweight-IP%2Ffwrisc","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Featherweight-IP%2Ffwrisc/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Featherweight-IP%2Ffwrisc/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Featherweight-IP%2Ffwrisc/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/Featherweight-IP","download_url":"https://codeload.github.com/Featherweight-IP/fwrisc/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":243809865,"owners_count":20351403,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["risc-v","verilog","zephyr"],"created_at":"2024-07-31T01:00:40.048Z","updated_at":"2025-03-16T00:32:16.413Z","avatar_url":"https://github.com/Featherweight-IP.png","language":"SystemVerilog","funding_links":[],"categories":["Open Source Core Implementations"],"sub_categories":[],"readme":"# FWRISC\n\n[![Build Status](https://dev.azure.com/mballance/mballance/_apis/build/status/mballance.fwrisc?branchName=master)](https://dev.azure.com/mballance/mballance/_build/latest?definitionId=8\u0026branchName=master)\n\n\nFWRISC-S is a _Featherweight RISC-V_ implementation of the RV32IMC instruction set with\nIoT-appropriate security features. This implementation supports the integer instructions,\nregisters, CSRs, and exceptions as required by the RISC-V spec.\n\nThis revision of the core was created for the 2019 RISC-V security contest:\nhttps://riscv.org/2019/07/risc-v-softcpu-core-contest/\n\nFWRISC is a non-pipelined processor that aims to balance performance with FPGA resource utilization. \nIt achieves 0.15 DMIPS/Mhz.\n\nFWRISC correctly runs all RISCV RV32I [compliance tests](https://github.com/riscv/riscv-compliance).\nIt also supports the [Zephyr](https://www.zephyrproject.org/) RTOS.\n\n## Core Features\n\n- RV32IMC instructions\n- Multi-cycle shift\n- Multi-cycle multiply/divide\n- Support for the compressed-instruction ISA\n- MINSTR, MCYCLE counters\n- ECALL/EBREAK/ERET instrutions\n- Support for address-alignment exceptions\n\n## SEcurity Features\nFWRISC-S implements Data Execution Prevention, as a way to prevent arbitrary code\nexecution. While more-complex protection techniques are appropriate for more-complex\nsystems, IoT systems typically run a fixed program that can be easily protected in\nthis way. \nThe Zephyr SoC-support configuration has been setup such that data execution prevention\nis configured just after kernel boot. Using linker symbols, the configuration\nprograms CSRs to only allow execution in the text section of the image. See \n[Zephyr](doc/fwrisc_zephyr.md) for more information.\n\n## Resource Stats\nThe bare FWRISC-S 1.0.0 core consumes the following resources:\n\n\u003ctable border=\"1\"\u003e\n\u003ctr\u003e\n\u003cth\u003eTarget\u003c/th\u003e\u003cth\u003eLUTs/LCs\u003c/th\u003e\u003cth\u003eRAM\u003c/th\u003e\u003cth\u003eFrequency\u003c/th\u003e\n\u003c/tr\u003e\n\u003ctr\u003e\u003ctd\u003eMicrosemi IGLOO2 (Synplify)\u003c/td\u003e\u003ctd\u003e2592 LUTs\u003c/td\u003e\u003ctd\u003e2x 64x18\u003c/td\u003e\u003ctd\u003e36.6Mhz\u003c/td\u003e\u003c/tr\u003e\n\u003c/table\u003e\n\n## Getting Started\n\nSee the [Quickstart](doc/fwrisc_quickstart.md) document to get started with FWRISC. For more \ndetailed information, see the documents below.\n\n- [Tools](doc/fwrisc_tools.md)\n- [Setup](doc/fwrisc_setup.md)\n- [Verification Environment](doc/fwrisc_verification.md)\n- [Design Documents](doc/fwrisc_design.md)\n- [Zephyr Port](doc/fwrisc_zephyr.md)\n\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FFeatherweight-IP%2Ffwrisc","html_url":"https://awesome.ecosyste.ms/projects/github.com%2FFeatherweight-IP%2Ffwrisc","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FFeatherweight-IP%2Ffwrisc/lists"}