{"id":21782047,"url":"https://github.com/HEP-SoC/SoCMake","last_synced_at":"2025-07-19T17:31:20.583Z","repository":{"id":238818627,"uuid":"774482172","full_name":"HEP-SoC/SoCMake","owner":"HEP-SoC","description":"CMake based hardware build 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align=\"center\"\u003e\n\u003cimg src=\"docs/static/img/SoCMakeLogo3.png\" alt=\"SoCMake\" width=\"40%\"\u003e\n\n  \u003ca href=\"https://hep-soc.github.io/SoCMake/\"\u003eDocumentation\u003c/a\u003e |\n  \u003ca href=\"https://github.com/HEP-SoC/SoCMake/tree/develop/examples\"\u003eExamples\u003c/a\u003e\n\u003c/h1\u003e\n\n\nIntroduction\n------------\n\nSoCMake is a library for CMake that adds support for hardware development.\nIt bridges the gap between software and hardware build flows, and allows for building complex System-on-Chip projects using a unified build system.\n\nUnlike other hardware build systems, SoCMake reuses the mature CMake infrastructure instead of building it from scratch, benefiting from decades of development that went into CMake.\n\nFeatures\n--------\n\nComparing to other build systems, SoCMake's biggest strength is first class support for C,C++ compilation and cross-compilation.\nSoCMake key features are:\n\n* First class C, C++ compilation support\n* Support for Cross-Compilation of (ARM, RiscV,...) application code.\n* Extensive HDL simulation support (Verilog, SystemVerilog, VHDL)\n* SystemC and SystemC-UVM support\n* Mixed-language SV-VHDL-SC simulation\n* SystemVerilog-UVM and VHDL-UVVM support\n* Software and IP block package managment with CMake package managers\n* HDL code generation and conversion (PeakRDL, desyrdl, yosys, sv2v, ..)\n* Build graph generation with graphviz\n\n\nGetting started\n---------------\n\nSoCMake is lightweight and has minimal dependencies.\nThe only mandatory dependencies are `CMake\u003e=3.25.0` and `make` ([Install Dependencies](https://hep-soc.github.io/SoCMake/docs/getting_started))\n\nThere is no need to install SoCMake on your system, it is possible to fetch it in your `CMakeLists.txt`\n\nCreate a file called `CMakeLists.txt`\n\n```CMake\n# Bootstrap SoCMake into CMake project\ninclude(FetchContent)\nFetchContent_Declare(SoCMake\n    GIT_REPOSITORY \"https://github.com/HEP-SoC/SoCMake.git\"\n    GIT_TAG develop)\nFetchContent_MakeAvailable(SoCMake)\n\ncmake_minimum_required(VERSION 3.25) # CMake minimum required version\nproject(adder NONE)                  # Name of CMake project\n\n# Create an IP block called adder\nadd_ip(adder)  \n# Add verilog file adder.v to adder IP\nip_sources(adder VERILOG\n                 ./adder.v)\n# Create a target for Icarus Verilog\niverilog(adder)\n```\n\nThe directory structure should be as following:\n\n```\nadder/\n├── adder.v\n└── CMakeLists.txt\n```\n\nIn order to run the simulation execute the following:\n```\nmkdir build \u0026\u0026 cd build\ncmake ../\nmake run_adder_iverilog\n```\n\nThe following message should be printed:\n\n```\n[ 50%] Compile adder with iverilog\n[ 50%] Built target adder_iverilog\n[100%] Run iverilog testbench compiled from adder\nHello from Adder!\n[100%] Built target run_adder_iverilog\n```\n\nExamples\n--------\n\nFor more examples on how to use SoCMake including the previous example visit [Examples](https://github.com/HEP-SoC/SoCMake/tree/develop/examples).\nSome of the examples include:\n\n* Simple Verilog and VHDL testbenches\n* Mixed language simulation examples SystemVerilog-VHDL, SystemC-SystemVerilog\n* UVM-SystemC and SystemC examples\n* Verilator C++ and SystemC teshbench\n* Foreign Language Interfaces such as DPI-C, VHPIDirect\n\nAdditionally some more complex examples are available on separate repositories:\n\n* PicoRV32 testbench with cross-compilation of test firmware [picorv32-socmake](https://github.com/HEP-SoC/picorv32_socmake)\n* APB-CRC IP block with register file generated with PeakRDL-regblock and testbenches in [SystemC-UVM](https://github.com/Risto97/apb_crc_uvm_socmake/tree/master/sc-uvm) and [SystemVerilog-UVM](https://github.com/Risto97/apb_crc_uvm_socmake/tree/master/sv-uvm)\n* VHDL-UVVM [apb-crc](https://github.com/HEP-SoC/UVVM_SoCMake/tree/master/examples/apb_crc) testbench and [uart](https://github.com/HEP-SoC/UVVM_SoCMake/tree/master/examples/uart) testbench\n\n\nCheck out the [Documentation](https://hep-soc.github.io/SoCMake/)\n\nCheck out the [Pipeline Status (CDash)](https://my.cdash.org/index.php?project=SoCMake)\n","funding_links":[],"categories":["Build Systems","Other"],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FHEP-SoC%2FSoCMake","html_url":"https://awesome.ecosyste.ms/projects/github.com%2FHEP-SoC%2FSoCMake","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FHEP-SoC%2FSoCMake/lists"}