{"id":13648850,"url":"https://github.com/IntelLabs/riscv-vector","last_synced_at":"2025-04-22T11:33:20.078Z","repository":{"id":188288470,"uuid":"560679324","full_name":"IntelLabs/riscv-vector","owner":"IntelLabs","description":"Vector Acceleration IP core for RISC-V*","archived":false,"fork":false,"pushed_at":"2025-04-18T10:24:09.000Z","size":21802,"stargazers_count":175,"open_issues_count":0,"forks_count":25,"subscribers_count":6,"default_branch":"main","last_synced_at":"2025-04-19T00:17:15.045Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Scala","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mulanpsl-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/IntelLabs.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"License.MulanPSL2","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":"security.md","support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null}},"created_at":"2022-11-02T02:40:06.000Z","updated_at":"2025-04-13T12:41:52.000Z","dependencies_parsed_at":"2023-10-16T16:44:14.839Z","dependency_job_id":"8c695ff9-d1ff-4ff2-ae53-2d17ca3e315f","html_url":"https://github.com/IntelLabs/riscv-vector","commit_stats":null,"previous_names":["intellabs/riscv-vector"],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/IntelLabs%2Friscv-vector","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/IntelLabs%2Friscv-vector/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/IntelLabs%2Friscv-vector/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/IntelLabs%2Friscv-vector/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/IntelLabs","download_url":"https://codeload.github.com/IntelLabs/riscv-vector/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":250232551,"owners_count":21396661,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-02T01:04:36.398Z","updated_at":"2025-04-22T11:33:19.519Z","avatar_url":"https://github.com/IntelLabs.png","language":"Scala","funding_links":[],"categories":["Scala"],"sub_categories":[],"readme":"# riscv-vector\nVector Acceleration IP core for RISC-V*.  \n## Introduction\nVector Acceleration IP core for RISC-V* is a flexible RISC-V Vector unit that aims to support RISC-V Vector extension. The interface is based on OVI (Open Vector Interface) in order to integrate with different scalar cores. The code is written with Chisel. \n## Status\nSo far, the arithmetic functional units are sufficiently tested. Other functions such as load/store and control flow only passed basic test.\n\n\u003e Arithmetic FUs are located at *src/main/scala/darecreek/exu/vfucore/*, which contains 64-bit FU cores (mask and permutation are VLEN-bit). You can write a wrapper to compose multiple 64-bit FUs into one VLEN-bit FU. In this project, the *exu/lanevfu* and *exu/crosslane* are FU wrappers (with VLEN=256).\n\n**Note**: this project is suspended now.\n\n\n## Architecture\nAs shown below, it is an out-of-order vector core with OVI interface (orange arrows). There are one arithmetic issue queue and one load/store issue queue, which can operate simultaneously. Each issue queue issues micro-ops in order, but it can be modified to out-of-order issuing potentially. \n\n\u003cp align=\"center\"\u003e\n\u003cimg src=\"doc/img/vpu_top.jpg\" width=\"80%\" height=\"80%\"\u003e\n\u003c/p\u003e\n\nPlease refer to [Design Introduction](./doc/design.md) for more details.\n\n\n## License\nOnly the OVI(Open Vector Interface) is under Solderpad Hardware License v2.1 and others follow the Mulan PSL v2.  \n    \n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FIntelLabs%2Friscv-vector","html_url":"https://awesome.ecosyste.ms/projects/github.com%2FIntelLabs%2Friscv-vector","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FIntelLabs%2Friscv-vector/lists"}