{"id":13408016,"url":"https://github.com/LeiWang1999/FPGA","last_synced_at":"2025-03-14T12:31:59.280Z","repository":{"id":37673432,"uuid":"275109321","full_name":"LeiWang1999/FPGA","owner":"LeiWang1999","description":"帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目","archived":false,"fork":false,"pushed_at":"2022-05-15T11:38:02.000Z","size":60,"stargazers_count":3905,"open_issues_count":2,"forks_count":658,"subscribers_count":64,"default_branch":"master","last_synced_at":"2024-10-14T15:21:32.387Z","etag":null,"topics":["fpga","pynq","verilog","vivado","xilinx"],"latest_commit_sha":null,"homepage":"","language":null,"has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/LeiWang1999.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"license/Readme.md","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2020-06-26T08:31:36.000Z","updated_at":"2024-10-14T15:17:23.000Z","dependencies_parsed_at":"2022-07-13T15:59:46.693Z","dependency_job_id":null,"html_url":"https://github.com/LeiWang1999/FPGA","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/LeiWang1999%2FFPGA","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/LeiWang1999%2FFPGA/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/LeiWang1999%2FFPGA/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/LeiWang1999%2FFPGA/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/LeiWang1999","download_url":"https://codeload.github.com/LeiWang1999/FPGA/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":243578402,"owners_count":20313824,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["fpga","pynq","verilog","vivado","xilinx"],"created_at":"2024-07-30T20:00:50.189Z","updated_at":"2025-03-14T12:31:58.504Z","avatar_url":"https://github.com/LeiWang1999.png","language":null,"funding_links":[],"categories":["Awesome Awesome ⭐","硬件_其他","Others"],"sub_categories":["*ASIC Design Cycle Work \"PnR\":*","网络服务_其他"],"readme":"\u003ch1 align=\"center\"\u003eFPGA Tutorial \u003c/h1\u003e\n\n本项目旨在**帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目**。\n\n[一起为本项目作出贡献](#github)\n\n\u003ch2 align=\"center\"\u003e零、镜像下载\u003c/h2\u003e\n\n- [Vivado 多版本安装包 百度网盘](https://pan.baidu.com/s/1op98YUPNqSfqAN2UeywlNA)（提取码：DZKR）\n- [Vivado License](https://github.com/LeiWang1999/FPGA/tree/master/license)\n- [PetaLinux 2017.4](https://pan.baidu.com/s/1xZVsQVMPowDfQhBysLQ-1A)(提取码：rlcv)\n- [pynq_rootfs-arm_v2.4-2.5](https://pan.baidu.com/s/1JFgg0Pezk0mBub8zMdcYyA)（提取码：rn0h）\n- [Ubuntu-16.04.2-minimal-armhf-2017-06-18](https://pan.baidu.com/s/1mMWF8H2xEtbE5ayJ7pdGTw)(提取码：nckh)\n\n\u003ch2 align=\"center\"\u003e一、入门资料\u003c/h2\u003e\n\n\u003ch3\u003eFPGA相关门户网站\u003c/h3\u003e\n\n- [Xilinx](https://www.xilinx.com/)\n- [Xilinx Wiki](https://xilinx-wiki.atlassian.net/wiki/spaces/A/overview)\n- [Xilinx Forums](https://forums.xilinx.com/)\n- [Xilinx Open Hardware](http://www.openhw.org/)\n- [电子创新网Xilinx社区](http://xilinx.eetrend.com/)\n- [Altera](https://www.intel.cn/content/www/cn/zh/products/programmable.html)\n- [Digilent 中国](http://www.digilent.com.cn/)\n- [米联客](https://www.uisrc.com/portal.php)\n- [opencores 开源硬件IP站](https://opencores.org/)\n- [FPGA FOR FUN](https://www.fpga4fun.com/CrossClockDomain.html)\n- [HDLBits](https://hdlbits.01xz.net/wiki/Main_Page)\n\n\u003ch3 id=\"github\"\u003e每个人都应该会使用GitHub\u003c/h3\u003e\n\n- [廖雪峰的Git教程]( https://www.liaoxuefeng.com/wiki/896043488029600 )\n- [Github Guides](https://guides.github.com/activities/hello-world/)\n- [如何参与到本项目的建设](docs/HowContribute.md)\n\n\u003ch3\u003e数字电路\u003c/h3\u003e\n\n数字电路是学习FPGA的前提。\n\n如果没有学习过数字电路，先选择一本数字电路教程(下面的数字电路课本中选一本，或者用手头的数字电路课本),再选择一本Verilog教程。用Verilog实现一遍数字电路里的加法器等等，是很好的入门经历。\n\n- [电子技术基础 数字部分 (康华光.第5版)](http://leiblog.wang/static/FPGA/books/电子技术基础.数字部分.(康华光.第5版).pdf)\n\n\u003ch3\u003eVerilog HDL入门\u003c/h3\u003e\n\n\u003e HDL是硬件描述语言(Hardware Design Language)，使用这门语言的时候我们像是在**建模**，这点区别于编程语言，这往往是新手首先需要绕过来的难关！\n\u003e\n\u003e Xilinx和Altera是我们主要使用到的FPGA芯片厂商，此外还有国产的紫光、安陆等。对我们用户来说，他们的区别主要在于EDA软件的不同，比如Xilinx使用的是Vivado、Altera使用的是Quatus...\n\u003e\n\u003e 我个人认为Vivado的功能最强大，最好用，但缺点在于综合、生成等步骤的速度慢，你需要一台好的电脑！\n\u003e\n\u003e 虽然对于学习Verilog来说他们没有差别，但学习FPGA的时候手上最好要有一块板卡，上板验证会有更多的成就感。所以，用什么家的板卡，就用什么软件。\n\n- 经典图书\n  - [搭建你的数字积木](https://book.douban.com/subject/30242443/)\n    - Xilinx大学计划书目，比较推荐，但是没找到PDF,并且还有配套的Basys3/EGO1例程([仓库地址](https://github.com/xupsh/Digital-Design-Lab))\n  - [Verilog数字系统设计教程 夏宇闻](http://leiblog.wang/static/FPGA/books/Verilog数字系统设计教程夏宇闻.pdf)\n  - [Verilog经典教程 夏宇闻](http://leiblog.wang/static/FPGA/books/夏宇闻-Verilog经典教程.pdf)\n  - [深入浅出FPGA](http://leiblog.wang/static/FPGA/books/深入浅出FPGA.pdf)\n  - [Vivado使用误区与进阶](https://leiblog.wang/static/FPGA/books/Vivado使用误区与进阶.pdf)\n  - [Xilinx应用进阶 调用IP核详解和设计开发](https://leiblog.wang/static/FPGA/books/Xilinx%20FPGA%E5%BA%94%E7%94%A8%E8%BF%9B%E9%98%B6%20%20%E9%80%9A%E7%94%A8IP%E6%A0%B8%E8%AF%A6%E8%A7%A3%E5%92%8C%E8%AE%BE%E8%AE%A1%E5%BC%80%E5%8F%91%20[%E9%BB%84%E4%B8%87%E4%BC%9F%E7%BC%96%E8%91%97][%E7%94%B5%E5%AD%90%E5%B7%A5%E4%B8%9A%E5%87%BA%E7%89%88%E7%A4%BE][2014.08][274%E9%A1%B5].pdf)\n  \n- 网路上生动的大神教程\n  - [Artix7修炼秘籍](http://leiblog.wang/static/FPGA/books/00《Artix7修炼秘籍》-MIA701第一季.pdf)\n  - [Verilog那些事儿](http://leiblog.wang/static/FPGA/books/Verilog那些事儿/)\n    - [驱动篇](http://leiblog.wang/static/FPGA/books/Verilog那些事儿/02Veilog那些事儿-驱动篇I.pdf)\n    - [时续篇](http://leiblog.wang/static/FPGA/books/Verilog那些事儿/03Verilog_HDL_那些事儿_时序篇v2.pdf)\n    - [建模篇](http://leiblog.wang/static/FPGA/books/Verilog那些事儿/04VerilogHDL那些事儿_建模篇.pdf)\n    - [整合篇](http://leiblog.wang/static/FPGA/books/Verilog那些事儿/05VerilogHDL那些事儿-整合篇.pdf)\n  - [Xilinx原语的使用方法](http://leiblog.wang/static/FPGA/books/xilinx原语的使用方法.pdf)\n  - [FPGA自学笔记-设计与验证](http://leiblog.wang/static/FPGA/books/FPGA自学笔记——设计与验证公开版.pdf)\n  - [Verilog开发经验总结](http://leiblog.wang/static/FPGA/books/Verilog开发经验总结.pdf)\n  - [猫叔的FPGA时序约束教程](https://leiblog.wang/static/FPGA/books/%E7%8C%AB%E5%8F%94%E7%9A%84FPGA%E6%97%B6%E5%BA%8F%E7%BA%A6%E6%9D%9F%E6%95%99%E7%A8%8B.pdf)\n  - [Xilinx系列FPGA芯片IP核详解](https://leiblog.wang/static/FPGA/books/Xilinx%E7%B3%BB%E5%88%97FPGA%E8%8A%AF%E7%89%87IP%E6%A0%B8%E8%AF%A6%E8%A7%A3_%E5%88%98%E4%B8%9C%E5%8D%8E%E7%BC%96%E8%91%97.pdf)\n  - [数字集成电路静态时序分析基础](https://www.bilibili.com/video/BV1if4y1p7Dq)\n  - [综合与Design Compiler](http://leiblog.wang/static/FPGA/books/综合与DesignCompiler.pdf)\n- 官方pdf文档\n  - [Vivado从此开始](http://leiblog.wang/static/FPGA/books/Vivado从此开始/)\n  - [Verilog HDL程序设计与实践 Xilinx大学计划](http://leiblog.wang/static/FPGA/books/VerilogHDL程序设计与实践.pdf)\n- Xilinx 入门视频\n  - [Digilent Basys3 手把手教学](https://space.bilibili.com/511019924/channel/detail?cid=134957)\n    - 顺便学一下Vivado如何使用\n  - [Vivado SDK工程移植到Vitis](https://forums.xilinx.com/t5/Xilinx-%E4%BA%A7%E5%93%81%E8%AE%BE%E8%AE%A1%E4%B8%8E%E5%8A%9F%E8%83%BD%E8%B0%83%E8%AF%95%E6%8A%80%E5%B7%A7/%E5%B0%86%E8%B5%9B%E7%81%B5%E6%80%9D-SDK-%E5%B7%A5%E7%A8%8B%E7%A7%BB%E6%A4%8D%E5%88%B0-Vitis-%E7%9A%84%E5%88%86%E6%AD%A5%E6%8C%87%E5%8D%97/ba-p/1066332)\n- Altera 入门视频\n  - [正点原子 FPGA教学](https://www.bilibili.com/video/BV1Mb411E7gd?from=search\u0026seid=11737352508875302131)\n    - 如果买的是正点原子家的FPGA，可以白嫖很多项目。\n    - 别家的FPGA，学习语法、驱动，也是没问题的。\n  - [芯航线 FPGA从零到入门](https://www.bilibili.com/video/BV1tW411v78j?from=search\u0026seid=11737352508875302131)\n\n\u003ch3\u003e飞速提升开发效率✈️\u003c/h3\u003e\n\n- [VsCode取代Vivado自带编辑器](https://editor.csdn.net/md/?articleId=84668833)\n- [使用板卡文件自动配置环境(板卡芯片、DDR等)](https://www.bilibili.com/s/video/BV1zg4y1q7Jd)\n  - [EGO1板卡文件]( https://github.com/LeiWang1999/FPGA/boards)\n  - [Digilent Boards 全家桶]( https://github.com/Digilent/vivado-boards)\n- [ModelSim与Matlab搭建图像仿真环境(无需上板即可验证Verilog算法!)](http://leiblog.wang/technicaldetail/5e397c7937a947e1fa893314)\n- [Python实现Vivado和ModelSim仿真自动化](https://mp.weixin.qq.com/s/LvmzGJt4ywOUXO7TfyPtcg)\n- [SystemVerilog与功能验证](https://leiblog.wang/static/FPGA/books/SystemVerilog%E4%B8%8E%E5%8A%9F%E8%83%BD%E9%AA%8C%E8%AF%81%C2%81.pdf)\n\n\u003ch3\u003e规范你的工程🌟\u003c/h3\u003e\n\n- [华为verilog编程规范](http://leiblog.wang/static/FPGA/books/standard/华为verilog编程规范.pdf)\n- [IEEE_Verilog](http://leiblog.wang/static/FPGA/books/standard/IEEE_Verilog.pdf)\n\n\u003ch3\u003e商业报告\u003c/h3\u003e\n\n- [电子设备-电子行业专题报告：国产FPGA研究框架-方正证券](https://leiblog.wang/static/FPGA/books/%E7%94%B5%E5%AD%90%E8%AE%BE%E5%A4%87-%E7%94%B5%E5%AD%90%E8%A1%8C%E4%B8%9A%E4%B8%93%E9%A2%98%E6%8A%A5%E5%91%8A%EF%BC%9A%E5%9B%BD%E4%BA%A7FPGA%E7%A0%94%E7%A9%B6%E6%A1%86%E6%9E%B6-%E6%96%B9%E6%AD%A3%E8%AF%81%E5%88%B8[%E9%99%88%E6%9D%AD]-20201018%E3%80%90113%E9%A1%B5%E3%80%91.pdf)\n\n\u003ch2 align=\"center\"\u003e二、进阶资料\u003c/h2\u003e\n\u003ch3\u003eSOC System on Chip\u003c/h3\u003e\n\n\u003e Xilinx系列最全最详细的文档其实是官方提供的 [Xilinx Docnav](https://china.xilinx.com/support/documentation-navigation/overview.html)\n\u003e\n\u003e https://www.zhihu.com/question/56596019\n\n- [MicroBlaze](https://china.xilinx.com/products/design-tools/microblaze.html)\n\n- ZYNQ\n  - [UG 585 最权威的官方文档](https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf)\n  - [The ZYNQ Book](http://www.zynqbook.com/)\n  - [The ZYNQ Book 中文版](http://leiblog.wang/static/FPGA/books/The_Zynq_Book_ebook_chinese.pdf)\n  - [MicroZed 300多篇教学博客](http://adiuvoengineering.com/microzed-chronicles/?tdsourcetag=s_pctim_aiomsg)\n  - [米联客 SOC 修炼秘籍](http://leiblog.wang/static/FPGA/books/ZYNQ/%E7%B1%B3%E8%81%94%E3%80%8AZYNQ%20SOC%E4%BF%AE%E7%82%BC%E7%A7%98%E7%B1%8D%E3%80%8B.pdf)\n\n- [PYNQ](http://www.pynq.io/)\n  - [Github](https://github.com/Xilinx/Pynq)\n  - [xupsh pynqdoc](https://github.com/xupsh/pynqdoc)\n  - [Docs](https://pynq.readthedocs.io/en/v2.5.1/)\n  - [DIscuss](https://discuss.pynq.io/)\n  - [PYNQ Z1 Digilent 中文指导手册](https://digilent-china.gitbook.io/)\n  - [PYNQ 镜像制作](https://pynq.readthedocs.io/en/latest/pynq_sd_card.html#prepare-the-building-environment)\n\n\u003ch3\u003eHLS 高层次综合\u003c/h3\u003e\n\n- [Xilinx 官方教程](http://xilinx.eetop.cn/list-83-1.html)\n\n- [FPGA 并行编程](https://github.com/xupsh/pp4fpgas-cn)\n\n- [Vivado HLS 基本应用与图像处理](https://www.bilibili.com/video/BV11b411e7m3)\n\n\n\u003ch3\u003e计算机体系结构\u003c/h3\u003e\n\n- [Chisel 学习路线](https://blog.csdn.net/qq_34291505/article/details/86744581)\n\n- [Chisel Book Chinese](http://www.imm.dtu.dk/~masca/chisel-book-chinese.pdf)\n\n- [Chisel 入门资料](https://zhuanlan.zhihu.com/p/98097268)\n\n- [CPU自制入门](http://leiblog.wang/static/FPGA/books/CPU自制入门.pdf)\n\n- [手把手教你设计CPU——RISC-V处理器篇](https://leiblog.wang/static/FPGA/books/%E3%80%8A%E6%89%8B%E6%8A%8A%E6%89%8B%E6%95%99%E4%BD%A0%E8%AE%BE%E8%AE%A1CPU%E2%80%94%E2%80%94RISC-V%E5%A4%84%E7%90%86%E5%99%A8%E7%AF%87%E3%80%8B.pdf)\n\n- [riscv-soc-book](https://github.com/cnrv/riscv-soc-book)\n\n- [RISC-V 2020 Digilent](http://www.digilent.com.cn/community/697.html)\n\n\u003ch3\u003e深度神经网络加速器\u003c/h3\u003e\n\n- [PYNQ_Classification](https://leiblog.wang/static/FPGA/books/Accelerator/PYNQ_CLASSIFICATION.pdf)\n\n- [深度学习加速器设计与实验](https://www.bilibili.com/video/BV1ih411o7Yy?from=search\u0026seid=3168767736458572847)\n\n- [NVDLA](http://nvdla.org/)\n\n- [VTA](https://tvm.apache.org/docs/vta/)\n\n\u003ch3\u003e硬件驱动\u003c/h3\u003e\n\n- [AC620以太网驱动 芯航线](http://leiblog.wang/static/FPGA/books/HardwareDriver/AC620以太网设计与应用教程V1.0.pdf)\n\n- [Video Series 教你如何搭建视频通路](https://forums.xilinx.com/t5/Video-and-Audio/Xilinx-Video-Series/td-p/849583)\n\n- [UART](https://mp.weixin.qq.com/s?__biz=MzI4NjE3MzUwMA==\u0026mid=2652138569\u0026idx=1\u0026sn=0fd5b6a75dd563bcc0a4480c8d095179\u0026chksm=f0003c1ac777b50cff872bb53840fdc52a6f53bcef523cb5ecdf94aa3371fc398edfdf1b7807\u0026token=1263105418\u0026lang=zh_CN\u0026scene=21#wechat_redirect)\n\n- [IIC](https://mp.weixin.qq.com/s?__biz=MzI4NjE3MzUwMA==\u0026mid=2652139704\u0026idx=1\u0026sn=817b2e70e4dc7ac3dd20db5306271ccd\u0026chksm=f00020ebc777a9fda8234e95fd00d1c1fdc64fbbac4af9b03b63dbb2df8573fb8ac40a189810\u0026scene=21#wechat_redirect)\n\n- [SPI](https://mp.weixin.qq.com/s?__biz=MzI4NjE3MzUwMA==\u0026mid=2652139702\u0026idx=1\u0026sn=c4b450e0913083e6e4d5db29a410924f\u0026chksm=f00020e5c777a9f356ebd73fe9c0699c606f346d8c82d54e67e036d94a57f90edbce37fa5039\u0026scene=21#wechat_redirect)\n\n- [CAN](https://mp.weixin.qq.com/s?__biz=MzI4NjE3MzUwMA==\u0026mid=2652138778\u0026idx=1\u0026sn=144a45d6f49f51613a399eac5ff7a257\u0026chksm=f0003d49c777b45fa9dc06810638906f5fead6acc311b450c96d541f3cd44f35869809d722fd\u0026token=272554766\u0026lang=zh_CN\u0026scene=21#wechat_redirect)\n\n\u003ch3\u003e操作系统\u003c/h3\u003e\n\n- [Petalinux 中文文档](https://china.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/c_ug1144-petalinux-tools-reference-guide.pdf)\n\n### 还得是B站\n\n- [数字集成电路静态时序分析基础](https://www.bilibili.com/video/av290295377)\n\n  想知道电路运行的最大频率吗？\n\n- [数字芯片设计基础](https://www.bilibili.com/video/BV12V411r7BD/)\n\n### 还得是知乎\n\n- [为什么ASIC的频率可以达到GHz，而FPGA只能达到几百MHz？](https://www.zhihu.com/question/51179323/answer/124680433)\n- [Github 上有哪些优秀的 Verilog/FPGA 项目？](https://www.zhihu.com/question/348990787/answer/2486699396)\n\n### 还得是steam\n\n- [SHENZHEN I/O](https://store.steampowered.com/app/504210/SHENZHEN_IO/?l=tchinese)\n\n\n\u003ch2 align=\"center\"\u003e三、优秀项目\u003c/h2\u003e\n\u003ch3\u003e官方开源项目\u003c/h3\u003e\n\n- [ADI 超多开源HDL库](https://github.com/analogdevicesinc/hdl)\n\n- [ALINX 黑金 官方仓库 (包含OV系列摄像头驱动、DDR驱动等)](https://github.com/alinxalinx)\n  - [AC616](https://github.com/alinxalinx/AC616)\n  - [AX4010](https://github.com/alinxalinx/AX4010)\n  - [AX7035](https://github.com/alinxalinx/AX7035)\n  - [AX309](https://github.com/alinxalinx/AX309)\n  - [AX7101](https://github.com/alinxalinx/AX7101)\n  - [AX7102](https://github.com/alinxalinx/AX7102)\n  - [AX7103](https://github.com/alinxalinx/AX7103)\n  - [AX7021](https://github.com/alinxalinx/AX7021)\n  - [AX7010](https://github.com/alinxalinx/AX7010)\n  - [AX301](https://github.com/alinxalinx/AX301)\n  - [AX7020](https://github.com/alinxalinx/AX7020)\n  - [AX7015](https://github.com/alinxalinx/AX7015)\n- [Digilent 官方仓库](https://github.com/Digilent)\n  - [vivado-library 很多好用的IP-VGA、HDMI等](https://github.com/Digilent/vivado-library)\n  - [vivado-boards Digilent开发板的板卡文件](https://github.com/Digilent/vivado-boards)\n    - [使用板卡文件，让你的设计事半功倍](https://www.bilibili.com/s/video/BV1zg4y1q7Jd)\n  - [Digilent 大神用户们的项目](http://www.digilent.com.cn/project/all/open.html)\n- [赛灵思中文学习资料和开源设计](https://github.com/xupsh)\n  - [74LSXX 芯片IP](https://github.com/xupsh/Digital-Design-Reference-Design/tree/dd239f50d5117917479b7a3b51eeb8a0d6945cc9/Library/74LSXX_Lib)\n\n\u003ch3\u003e优秀开源项目 - 初级\u003c/h3\u003e\n\n- [Verilog Practice](https://github.com/xiaop1/Verilog-Practice)\n  - Verilog训练\n\n- [带闹钟功能的计数器](https://github.com/LeiWang1999/DigitalAlarmClock)\n  - 板卡:`Nexys4 DDR`\n  - 功能\n    - 支持I2S协议驱动的音响，接入耳机播放闹钟\n    - 支持VGA显示剩余时间\n    - 支持闹钟计数时钟变速(一倍速和五倍速)\n- [搭建你的数字积木 配套工程](https://github.com/xupsh/Digital-Design-Lab)\n  - 板卡:`Basys3`|`EGO-1`\n  - 配套图书:[搭建你的数字积木](https://book.douban.com/subject/30242443/)\n\n\u003ch3\u003e优秀开源项目 - 中级\u003c/h3\u003e\n\n- [基于FPGA的机器博弈五子棋游戏](https://github.com/Starrynightzyq/ZYNQ-PYNQ-Z2-Gobang)\n  - 板卡:`PYNQ-Z2`\n  - 2018全国大学生FPGA创新设计邀请赛一等奖、最佳创意奖\n- [CM3软核 FPGA 车牌识别系统](https://github.com/Starrynightzyq/Nexys4DDR-ARM-M3-Plate-Recognition)\n  - 板卡:`Nexys4 DDR`\n  - 全国大学生集成电路创新创业大赛参赛作品\n- [Yolov2加速器设计](https://github.com/dhm2013724/yolov2_xilinx_fpga)\n  - 板卡:`PYNQ-Z2|ZedBoard|ZCU102`\n  - 很不错的加速器设计方案\n- [Pynq Accelerator](https://github.com/LeiWang1999/Pynq-Accelerator)\n  - 板卡:`PYNQ-Z1`\n- [ZYNQ NVDLA](https://github.com/LeiWang1999/ZYNQ-NVDLA)\n  - 板卡：`ZYNQ 7045 | ZCU 102`\n  - 开源加速器的解决方案、**可以跑任意网络！**\n- [FPGA Support for Vscode](https://github.com/Bestduan/fpga_support_plug)\n  - 北邮的一个大佬开源的Vscode写FPGA的项目\n\n\u003ch3\u003e优秀开源项目 - 高级\u003c/h3\u003e\n\n- [PYNQ集群 类脑计算](https://github.com/OpenHEC/SNN-simulator-on-PYNQcluster)\n  - 板卡:`PYNQ`\n  - 全国大学生FPGA创新设计作品\n- [basicmi/AI Chip](https://github.com/basicmi/AI-Chip)\n  - 关于 AI 芯片的跟踪report仓库\n\n\u003ch2 align=\"center\"\u003e四、推荐群组\u003c/h2\u003e\n\n1. \u003cOpnFPGA/IC攻城狮\u003e\n- 类型：QQ群\n- 群号：915880054\n- 备注：碎碎思大佬的群，主要是分享资料的，进群可以转微信群，那边很活跃。\n\n2. \u003cVerilog编程艺术\u003e\n- 类型：QQ群\n- 群号：361820636\n- 备注：群主几百年没有出现过了，也没有管理员，时常有广告\n\n3. \u003cverilog vhdl fpga入门进阶\u003e\n- 类型：QQ群\n- 群号：1140582958\n- 备注：1000人大群\n\n4. \u003c摸鱼范式-2022届数字IC\u003e\n- 类型：QQ群\n- 群号：1060380138\n- 备注：“摸鱼范式”公众号的群，2000人群\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FLeiWang1999%2FFPGA","html_url":"https://awesome.ecosyste.ms/projects/github.com%2FLeiWang1999%2FFPGA","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FLeiWang1999%2FFPGA/lists"}