{"id":13645488,"url":"https://github.com/MIPT-ILab/mipt-mips","last_synced_at":"2025-04-21T14:31:26.129Z","repository":{"id":93377318,"uuid":"42990634","full_name":"MIPT-ILab/mipt-mips","owner":"MIPT-ILab","description":"Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs","archived":true,"fork":false,"pushed_at":"2022-06-11T19:37:44.000Z","size":118657,"stargazers_count":341,"open_issues_count":40,"forks_count":139,"subscribers_count":23,"default_branch":"main","last_synced_at":"2024-11-09T18:42:48.486Z","etag":null,"topics":["branch-prediction","branch-predictor","clock-precise","computer-architecture","computer-architecture-lesson","cpu","cpu-cache","cpu-model","mips","mips-binutils","mipt","optimizations","pipeline","pre-silicon","prediction-algorithms","risc","risc-v","simulation","simulator"],"latest_commit_sha":null,"homepage":"http://mipt-ilab.github.io/mipt-mips/","language":"C++","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/MIPT-ILab.png","metadata":{"files":{"readme":"readme.md","changelog":null,"contributing":"contributing.md","funding":null,"license":"license.md","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null}},"created_at":"2015-09-23T09:12:26.000Z","updated_at":"2024-10-30T02:24:36.000Z","dependencies_parsed_at":null,"dependency_job_id":"f4b76324-3d15-4445-9031-d201a23f2ad7","html_url":"https://github.com/MIPT-ILab/mipt-mips","commit_stats":null,"previous_names":[],"tags_count":16,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/MIPT-ILab%2Fmipt-mips","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/MIPT-ILab%2Fmipt-mips/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/MIPT-ILab%2Fmipt-mips/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/MIPT-ILab%2Fmipt-mips/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/MIPT-ILab","download_url":"https://codeload.github.com/MIPT-ILab/mipt-mips/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":250070173,"owners_count":21369839,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["branch-prediction","branch-predictor","clock-precise","computer-architecture","computer-architecture-lesson","cpu","cpu-cache","cpu-model","mips","mips-binutils","mipt","optimizations","pipeline","pre-silicon","prediction-algorithms","risc","risc-v","simulation","simulator"],"created_at":"2024-08-02T01:02:35.819Z","updated_at":"2025-04-21T14:31:24.277Z","avatar_url":"https://github.com/MIPT-ILab.png","language":"C++","funding_links":[],"categories":["C++"],"sub_categories":[],"readme":"[![Contributors](https://img.shields.io/github/contributors/mipt-ilab/mipt-mips?label=Contributors)](https://github.com/MIPT-ILab/mipt-mips/graphs/contributors)\n[![Total alerts](https://img.shields.io/lgtm/alerts/g/MIPT-ILab/mipt-mips.svg?logo=lgtm\u0026logoWidth=18)](https://lgtm.com/projects/g/MIPT-ILab/mipt-mips/alerts/)\n[![Language grade: C/C++](https://img.shields.io/lgtm/grade/cpp/g/MIPT-ILab/mipt-mips.svg?logo=lgtm\u0026logoWidth=18)](https://lgtm.com/projects/g/MIPT-ILab/mipt-mips/context:cpp)\n\n# MIPT-V / MIPT-MIPS\n\nMIPT-V / MIPT-MIPS is a pre-silicon simulator of MIPS and RISC-V CPU. It measures _performance_ of program running on CPU, thus taking best features of RTL and common functional simulation:\n* **Precision**. We provide cycle-accurate models of branch prediction unit, pipeline, and other hardware internals.\n* **Customization**. Cache size, branch prediction algorithms, and other parameters can be easily changed even to unfeasible modes.\n* **Simplicity**. Our source files are much more readable than RTL and independent on SDK and synthesis flow.\n* **Speed**. 2 MHz simulation frequency on Cascade Lake.\n* **Scalability**. Modularized structure allows integration of more microarchitecture configurations.\n\nSimulator can be used for different purposes:\n* Performance control of **software optimizations**: you may check what and why happened to IPC.\n* Pathfinding of **hardware optimizations**: you may easily integrate some nice feature to CPU model.\n* **Comparison** of hardware solutions from different vendors.\n* **Performance control** of developed or produced hardware.\n* **Education**: simulator is a nice experimental frog to study CPU internals and software development process.\n\nKey system-level features:\n* Compatibility with interactive [MARS](https://github.com/MIPT-ILab/mipt-mips/wiki/MARS-syscalls) system calls.\n* Interactive simulation with [GDB](https://github.com/MIPT-ILab/mipt-mips/wiki/Interactive-simulation-with-GDB)\n\nKey microarchitecture features:\n* Configurable [branch prediction unit](https://github.com/MIPT-ILab/mipt-mips/wiki/BPU-model) with several prediction algorithms\n* Configurable instruction cache\n* Interstage data bypassing\n\n### Topology visualization:\n[![Topology](https://raw.githubusercontent.com/wiki/MIPT-ILab/mipt-mips/topology.png)](https://github.com/MIPT-ILab/PipelineFlowchartVis)\n\n### Pipeline diagrams:\n[![Pipeline](https://raw.githubusercontent.com/wiki/MIPT-ILab/mipt-mips/visualizer.png)](https://github.com/MIPT-ILab/PipelineVis)\n\nMore details about internals are available on [Wiki](https://github.com/MIPT-ILab/mipt-mips/wiki/Home/).\n\nFor questions, use our [Discussions](https://github.com/MIPT-ILab/mipt-mips/discussions) page.\n\n## Requirements\n\nWe use C++20 features and Boost 1.71. Thus, you have to [use compilers](https://github.com/MIPT-ILab/mipt-mips/wiki/C-compilers) of these versions or newer:\n* GCC 11\n* Clang 13.0.0\n* Apple LLVM Version 13.1.6\n* MS Visual Studio 2019 16.8\n\n[Install Boost](https://github.com/MIPT-ILab/mipt-mips/wiki/Required-libraries) before building the project.\n\nTo work with RISC-V traces, you need to install RISC-V toolchain. Please follow [the official instruction](https://github.com/riscv/riscv-gnu-toolchain/blob/master/README.md).\n\nTo work with MIPS traces, you need to install MIPS binutils. Please follow [our manual](https://github.com/MIPT-ILab/mipt-mips/wiki/MIPS-binutils) if you are using Linux, OS X, or Windows.\n\nOur build system is CMake. You should install CMake 3.13.5 or higher.\nCheck [our Wiki page](https://github.com/MIPT-ILab/mipt-mips/wiki/CMake) to get more details about CMake.\nUsers of IDE (Visual Studio, Eclipse, CodeBlocks etc.) may generate project files with CMake as well.\n\nTo generate RISC-V opcodes, CMake uses Python. `python3` interpreter should be available in your environment.\n\n## Command line options\n\n### Standalone run options\n\n* `-b \u003cfilename\u003e` — provide path to ELF binary file to execute.\n* `-n \u003cnumber\u003e` — number of instructions to run. If omitted, simulation continues until halting system call or jump to `null` is executed.\n\n### ISA and system-level options:\n\n* `-I` — modeled ISA. Default version is `mars`.\n    * `mips32`, `mips64` — state-of-the-art MIPS\n    * `riscv32`, `riscv64`, `riscv128` — RISC-V with all instructions\n    * `spim`, `spim64` — simplified MIPS without delayed branches\n    * `mipsI`, `mipsII`, `mipsIII`, `mipsIV` — legacy MIPS versions\n* `-f` — enables functional simulation only\n* `--mars` — enables MARS-compatible mode of system calls\n\n### Outputs\n* `-l` — enables per-module output, for instance:\n    * `-l fetch,decode` — prints only fetch and decode stages\n    * `-l cpu` —  prints all stages\n    * `-l cpu,!mem` —  print all except mem stage\n* `-d` — enables output of functional simulator\n* `--tdump` — enables module topology dump into topology.json\n\n### Performance mode options\n\n#### Branch prediction\n* `--bp-mode` — prediction mode. Check supported modes in [manual](https://github.com/MIPT-ILab/mipt-mips/wiki/BPU-model)\n* `--bp-lru` — prediction replacement policy: _LRU_, _pseudo-LRU_, or _infinite_\n* `--bp-size` — branch prediction cache size (amount of tracked branch instructions)\n* `--bp-ways` — # of ways in branch prediction cache\n\n#### Instruction cache\n* `--icache-type` — instruction cache type: _LRU_, _pseudo-LRU_, _always-hit_, or _infinite_\n* `--icache-size` — instruction cache size in bytes\n* `--icache-ways` — # of ways in instruction cache\n* `--icache-line-size` — line size of instruction cache\n\n#### Execution pipeline\n* `--long-alu-latency` - number of execution stages required for long arithmetic instructions to be complete\n\n## Workflow example\n\n#### Clone\n  1. Check that your environment meets all the requirements above.\n  1. Clone repository with submodules: `git clone --recursive https://github.com/MIPT-ILab/mipt-mips.git`\n#### Build\nTo build simulator faster, we recommend to [install Ninja](https://github.com/ninja-build/ninja/wiki/Pre-built-Ninja-packages).\n  1. Create a **new** build directory somewhere, then cd into it: `mkdir /path/to/your/build/directory`\n  1. Go to the build directory: `cd /path/to/your/build/directory`\n  1. Run `cmake /path/to/mipt-mips/simulator -G \"Ninja\"` to configure CMake\n  1. Run `ninja` to get the `mipt-mips` binary file\n  1. If you changed some source code files, just type `ninja` to rebuild project\n#### Run\n  1. Now you can run simulation: `./mipt-mips -b /path/to/binary`\n  1. See more command line options in the paragraph below\n  1. To run all unit tests, call `ninja unit-tests \u0026\u0026 ctest --verbose -C Release` from your build directory.\n\n## Test Coverage Chart!\n\n[![Code Coverage](https://codecov.io/gh/MIPT-ILab/mipt-mips/branch/main/graphs/tree.svg)](https://codecov.io/gh/MIPT-ILab/mipt-mips)\n\n## About MIPT-V / MIPT-MIPS\n\n[![](https://github.com/MIPT-ILab/ca-lectures/blob/master/images/mipt-eng.jpg?raw=true)](https://mipt.ru/english)\n[![](https://github.com/MIPT-ILab/ca-lectures/blob/master/images/drec.gif?raw=true)](https://mipt.ru/drec/)\n[![Logo](https://avatars2.githubusercontent.com/u/13999586?s=100)](https://mipt-ilab.github.io/)\n\nThis project is a part of [ILab](https://mipt-ilab.github.io/) activity at [Moscow Institute of Physics and Technology](http://phystech.edu/) (MIPT).\n\nThe main goal of the project is to teach the students the computer architecture through development of a microprocessor implementing the [RISC-V](http://en.wikipedia.org/wiki/RISC-V) and [MIPS](http://en.wikipedia.org/wiki/MIPS32) instruction set in both functional and performance simulators.\n\n### May I contribute?\n\nYes, if you attend lectures on Computer Architecture. See our [contributing.md](contributing.md) file for details.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FMIPT-ILab%2Fmipt-mips","html_url":"https://awesome.ecosyste.ms/projects/github.com%2FMIPT-ILab%2Fmipt-mips","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FMIPT-ILab%2Fmipt-mips/lists"}