{"id":13649277,"url":"https://github.com/MJoergen/HyperRAM","last_synced_at":"2025-04-22T14:31:10.841Z","repository":{"id":84026274,"uuid":"445532960","full_name":"MJoergen/HyperRAM","owner":"MJoergen","description":"Portable HyperRAM controller","archived":false,"fork":false,"pushed_at":"2024-12-08T20:57:51.000Z","size":4405,"stargazers_count":54,"open_issues_count":3,"forks_count":14,"subscribers_count":6,"default_branch":"main_old","last_synced_at":"2025-04-18T10:26:39.672Z","etag":null,"topics":["altera","artix","avalon","fpga","hyperram","intel","lattice","modelsim","quartus","questa","questasim","vhdl","vivado","xilinx"],"latest_commit_sha":null,"homepage":"","language":"VHDL","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/MJoergen.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2022-01-07T13:37:25.000Z","updated_at":"2025-02-21T15:34:33.000Z","dependencies_parsed_at":"2024-05-06T15:18:04.986Z","dependency_job_id":"82245d16-bfba-455c-b456-d5755c312213","html_url":"https://github.com/MJoergen/HyperRAM","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/MJoergen%2FHyperRAM","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/MJoergen%2FHyperRAM/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/MJoergen%2FHyperRAM/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/MJoergen%2FHyperRAM/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/MJoergen","download_url":"https://codeload.github.com/MJoergen/HyperRAM/tar.gz/refs/heads/main_old","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":250258897,"owners_count":21400992,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["altera","artix","avalon","fpga","hyperram","intel","lattice","modelsim","quartus","questa","questasim","vhdl","vivado","xilinx"],"created_at":"2024-08-02T01:04:55.395Z","updated_at":"2025-04-22T14:31:05.833Z","avatar_url":"https://github.com/MJoergen.png","language":"VHDL","funding_links":[],"categories":["VHDL"],"sub_categories":[],"readme":"# HyperRAM\n\nThis repository contains a portable OpenSource HyperRAM controller for FPGAs written in VHDL.\nI'm writing my own implementation because I've looked at several other implementations, and\nthey all seemed lacking in various regards (features, stability, portability, etc.)\n\nThe HyperRAM controller in this repository is a complete rewrite from scratch,\nand is provided with a [MIT license](LICENSE).\n\nLearn more by reading the documentation in this repository or by browsing the companion website: https://mjoergen.github.io/HyperRAM/\n\n## Features\n\nThis implementation has support for:\n\n* Maximum HyperRAM clock speed of 100 MHz.\n* Variable latency.\n* Configuration registers read and write\n* Identification registers read\n* Automatic configuration of latency mode upon reset.\n* 16-bit [Avalon Memory Map interface](doc/Avalon_Interface_Specifications.pdf) including burst mode.\n* Written for VHDL-2008\n\nAll the source files for the HyperRAM controller are in the\n[src/hyperram](src/hyperram) directory, and all files needed for simulation are\nin the [simulation](simulation) directory.\n\nPorting to another platform may require hand-tuning of some clock parameters,\nsee the section on [porting](PORTING.md).\n\n## Example Design\n\nI'm testing this HyperRAM controller on the [MEGA65](https://mega65.org/)\nhardware platform (revision 3).  It contains the 8 MB HyperRAM chip ([link to\ndatasheet](doc/66-67WVH8M8ALL-BLL-938852.pdf)) from ISSI (Integrated Silicon\nSolution Inc.).  Specifically, the part number of the HyperRAM device on the\nMEGA65 is `IS66WVH8M8BLL-100B1LI`, which indicates a 64 Mbit, 100 MHz version\nwith 3.0 V supply and a single-ended clock.\n\nI've written a complete Example Design to test the HyperRAM controller on this\nMEGA65 platform. The additional source files needed for this are placed in the\n[src/Example_Design](src/Example_Design) directory.\n\n## Getting started\n\nThe [HyperRAM controller](src/hyperram/hyperram.vhd) has just two interfaces,\none for the external HyperRAM device and one for the client (user) of the\nHyperRAM. For the client interface I've chosen the [Avalon Memory\nMap](doc/Avalon_Interface_Specifications.pdf) protocol. This is an industry\nstandard and is easy to use. The interface width is 16 bits corresponding to\none word of the HyperRAM. The addressing is in units of words, not bytes.\n\nThe Avalon interface supports burst mode, where you can read or write multiple\nwords in a single HyperRAM transaction. Section 3.5.5 in the Avalon Memory Map\nspecification describes burst mode in detail.\n\nTo see an example of how to use the HyperRAM controller and how to connect it\nto the internal FPGA logic and to the external HyperRAM device, have a look at\nthe [Example_Design](src/Example_Design), specifically at the [top level\nfile](src/Example_Design/top.vhd) and the [trafic\ngenerator](src/Example_Design/trafic_gen.vhd).\n\nMake sure that you are aware of the necessity of\n[Tri-State-Buffering](PORTING.md#tri-state-buffering). It is good design practice\nto infer the tri-state buffers from the top-level file. \n\nThe HyperRAM configuration and identification registers can be accessed through\nthe same Avalon Memory Map interface via the following addresses:\n\n* `0x80000000` : Identification Register 0 (Read-only)\n* `0x80000001` : Identification Register 1 (Read-only)\n* `0x80000800` : Configuration Register 0  (Read-write)\n* `0x80000801` : Configuration Register 1  (Read-write)\n\n### Avalon Memory Map interface\n\nHere is a brief summary of the signals involved in the Avalon Memory Map\ninterface.  For full details, refer to Section 3 of the\n[specification](doc/Avalon_Interface_Specifications.pdf).\nThe HyperRAM controller uses \"Pipelined Read Transfer with Variable Latency\",\nsee section 3.5.4 and Figure 12, and supports burst mode, see section 3.5.5.\nIt does not use the \"waitrequestAllowance\" property.\n\nSignal          | Description\n--------------: | :---------\n`write`         | Asserted by client for one clock cycle when writing data to the HyperRAM\n`read`          | Asserted by client for one clock cycle when reading data from the HyperRAM\n`address`       | Address (in units of 16-bit words)\n`writedata`     | Data to write\n`byteenable`    | 1-bit for each byte of `writedata` to the HyperRAM\n`burstcount`    | Number of words to transfer\n`readdata`      | Data received from the HyperRAM\n`readdatavalid` | Asserted when data from the HyperRAM is valid\n`waitrequest`   | Asserted by the device when it is busy\n\n## Further reading\n\nThe following links provide additional information:\n\n* [Example Design](src/Example_Design/README.md)\n* [Porting guideline](PORTING.md)\n* [Detailed design description](src/hyperram/README.md)\n* [Simulation](simulation/README.md)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FMJoergen%2FHyperRAM","html_url":"https://awesome.ecosyste.ms/projects/github.com%2FMJoergen%2FHyperRAM","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FMJoergen%2FHyperRAM/lists"}