{"id":13709487,"url":"https://github.com/OpenHisiIpCam/hisi-initregtable-go-parser","last_synced_at":"2025-05-06T16:31:52.655Z","repository":{"id":122704011,"uuid":"246793186","full_name":"OpenHisiIpCam/hisi-initregtable-go-parser","owner":"OpenHisiIpCam","description":"HiSilicon SoC`s U-Boot initial register table parser into human readable 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align=\"center\"\u003ehisi-initregtable-go-parser\u003c/h3\u003e\n\n---\n\n\u003cp align=\"center\"\u003eHiSilicon SoC`s U-Boot initial register table parser into human readable format\u003c/p\u003e\n\u003cp align=\"center\"\u003e\u003cem\u003ePart of \u003ca href=\"https://www.openhisiipcam.org\"\u003eOpenHisiIpCam\u003c/a\u003e project\u003c/em\u003e\u003c/p\u003e\n\n## :eyeglasses: About\n\nThis small application has several goals: \n* Useful tool for low level HiSilicon ip camera SoCs initialization research (at least it is applicable for chips that use U-Boot 2010.06).\n* Example how cool and easy we can use machine readable SystemRDL described registers information (more information in [How does it work](#how_does_it_work) section).\n\nThis is example output (left bottom corner is data view before parsing):\n\n![hisi-initregtable-go-parser example screenshot](images/hisi-initregtable-go-parser-example.png)\n\nAs you can see, after parsing, for each item in registers initilization table we have following information:\n* **Operation** (WRITE, READ or DELAY).\n* **Register**, that is used by operation.\n* Register`s **fields**, that are affected.\n* Each field **value meaning**.\n\nFormat of initial registers table, questions why there is such table, how it works, how to extract it from ROM image and so on are a bit out of scope this document. \nMostly it will be useful for people, who already faced with HiSilicon`s U-Boot, somehow knows what is going on and \nlooking for additional tools other than those provided by the vendor.\nMore information you can find follow links in [Futher information](#futher_information) section.\n\n## :hammer: Usage\n\n### Build\n\nPrerequistives are go, python3\n\nClone repo with submodules:\n```console\nfoo@bar:~$ git clone --recurse-submodules https://github.com/OpenHisiIpCam/hisi-initregtable-go-parser\n```\nInstall dependencies (systemrdl-compiler)\n```console\nfoo@bar:~$ sudo make deps:\n```\nRun build:\n```console\nfoo@bar:~$ make\n```\n\n### Run\n\n```console\nfoo@bar:~$ ./hisi-initregtable-go-parser --help\nUsage of ./hisi-initregtable-go-parser:\n  -chip string\n    \tHiSilicon chip model name ( hi3516av200 hi3519v101 ) (default \"hiXXX\")\n  -file string\n    \tfile with reg data (default \"u-boot.bin\")\n  -offset int\n    \toffset of reg data in file\n  -size int\n    \tsize of reg data in file (default 4016)\n```\n\n```console\nfoo@bar:~$ ./hisi-initregtable-go-parser -file ./regbins/reg_info_hi3519v101.bin -chip hi3519v101 -offset 0 -size 4016\n```\n\nYou can evaluate [sample output](regbins/reg_info_hi3519v101.output).\n\n## :bulb: How does it work \u003ca name=\"how_does_it_work\"\u003e\u003c/a\u003e\n\n**TODO**\n\nOverall pipilene is following: `systemrdl sources -\u003e golang sources -\u003e final binary`.\n\nSystemRDL data is parsed and coverted in go source code by rdl_to_go.py.\nThere is regs.go source file, it describes structs for regsiter, field and field`s value and operations over these types. \nGenerated source is basicly instances of types defined in regs.go with data from rdl files.\n\nExample systemrdl:\n```\n...\n    reg {\n        name = \"APLL configuration register 0\";\n\n        field {\n            name = \"Level-2 output frequency divider of the APLL\";\n        } apll_postdiv2[30:28];\n\n        field {\n            name = \"Level-1 output frequency divider of the APLL\";\n        } apll_postdiv1[26:24];\n\n        field {\n            name = \"Decimal part of the APLL frequency multiplication coefficient\";\n        } apll_frac[23:0];\n\n    } PERI_CRG_PLL0 @ 0x0000;\n...\n```\nGoes into following golang code:\n```go\n//...\nvar registers = [...]register32{\n    register32{\n        addr: 0x12010000,\n        name: \"PERI_CRG_PLL0\",\n        desc: \"APLL configuration register 0\",\n        fields: []field{\n            field{\n                bitStart: 0,\n                bitEnd:   23,\n                name:     \"apll_frac\",\n                desc:     \"Decimal part of the APLL frequency multiplication coefficient\",\n            },\n            field{\n                bitStart: 24,\n                bitEnd:   26,\n                name:     \"apll_postdiv1\",\n                desc:     \"Level-1 output frequency divider of the APLL\",\n            },\n            field{\n                bitStart: 28,\n                bitEnd:   30,\n                name:     \"apll_postdiv2\",\n                desc:     \"Level-2 output frequency divider of the APLL\",\n            },\n        },\n    },\n    //...\n}\n```\n\u003e Most probably exact this implementation is not the best one. \n\u003e For some cases it is possible improve memory usage for register database and make register/field/value lookup faster.\n\nGeneration itself is just text manipulations. Such technique is simplest, ... **TODO**\n\nObviously the parser can be done in python3 as well as systemrdl-compiler, and step with golang can be eliminated,\nbut as our task were not only the parser itself, but also code generation test. \nOur main software is written mainly in golang and there are parts with massive conditional registers manipulation,\nso target was avoid magic like:\n\n```go\nutils.WriteDevMem32(0x20270110, 0x60FA0000)\nvar tempCode uint32 = utils.ReadDevMem32(0x20270114)\n```\nBut do something like this, as it makes less mental effort.\n```go\nregs.Addr(PERI_CRG79).Field(\"a7_sc_seled\").Set(\"mhz24\")\nvar tempCode uint32 = regs.Addr(SOME_TEMPERATURE).Read()\n```\n\n\n## :exclamation: Futher information \u003ca name=\"futher_information\"\u003e\u003c/a\u003e\n\nThis work was inspired by @kakigate`s [hisi-initregtable-parser](https://github.com/kakigate/hisi-initregtable-parser), \nalso repo contains useful detailed information about initregtable structure.\n\nAt the moment parser only partially covers hi3516av200 family (hi3519v101 and hi3516av200 chips), \nbut this is only a matter of filling the [register database](https://github.com/OpenHisiIpCam/registers-description),\nif you are interested your contribution will be appriciated!\n\nIf you are interested in HiSilicon based ip cameras research/development/etc \nyou can visit our [project`s website](https://www.openhisiipcam.org) and browse our [github repos](https://github.com/OpenHisiIpCam/).\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FOpenHisiIpCam%2Fhisi-initregtable-go-parser","html_url":"https://awesome.ecosyste.ms/projects/github.com%2FOpenHisiIpCam%2Fhisi-initregtable-go-parser","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FOpenHisiIpCam%2Fhisi-initregtable-go-parser/lists"}