{"id":13649278,"url":"https://github.com/OpenResearchInstitute/dvb_fpga","last_synced_at":"2025-04-22T14:31:12.156Z","repository":{"id":41519298,"uuid":"229336893","full_name":"OpenResearchInstitute/dvb_fpga","owner":"OpenResearchInstitute","description":"RTL implementation of components for DVB-S2 ","archived":false,"fork":false,"pushed_at":"2023-05-01T08:35:36.000Z","size":2004,"stargazers_count":111,"open_issues_count":6,"forks_count":33,"subscribers_count":50,"default_branch":"master","last_synced_at":"2024-11-10T00:32:55.272Z","etag":null,"topics":["bch-fec","dvb-s2","fpga","hacktoberfest","ldpc-codes","vhdl"],"latest_commit_sha":null,"homepage":"","language":"VHDL","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/OpenResearchInstitute.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null}},"created_at":"2019-12-20T21:10:51.000Z","updated_at":"2024-10-16T15:03:57.000Z","dependencies_parsed_at":"2024-01-14T11:00:17.856Z","dependency_job_id":"ba1c4f6d-de15-4232-af01-90ffb628b45b","html_url":"https://github.com/OpenResearchInstitute/dvb_fpga","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/OpenResearchInstitute%2Fdvb_fpga","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/OpenResearchInstitute%2Fdvb_fpga/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/OpenResearchInstitute%2Fdvb_fpga/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/OpenResearchInstitute%2Fdvb_fpga/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/OpenResearchInstitute","download_url":"https://codeload.github.com/OpenResearchInstitute/dvb_fpga/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":250258901,"owners_count":21400992,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["bch-fec","dvb-s2","fpga","hacktoberfest","ldpc-codes","vhdl"],"created_at":"2024-08-02T01:04:55.413Z","updated_at":"2025-04-22T14:31:07.148Z","avatar_url":"https://github.com/OpenResearchInstitute.png","language":"VHDL","funding_links":[],"categories":["VHDL"],"sub_categories":[],"readme":"# DVB FPGA\n\n[![Unit tests](https://github.com/OpenResearchInstitute/dvb_fpga/actions/workflows/main.yml/badge.svg)](https://github.com/OpenResearchInstitute/dvb_fpga/actions/workflows/main.yml)\n[![Synthesis](https://github.com/OpenResearchInstitute/dvb_fpga/actions/workflows/synth.yml/badge.svg)](https://github.com/OpenResearchInstitute/dvb_fpga/actions/workflows/synth.yml)\n\nThis project aims to implement RTL components for DVB-S2, initially focusing on\nthe transmission side.\n\n| ![System architecture](misc/system_architecture.png)                        |\n| :---:                                                                       |\n| Functional block diagram of the DVB-S2 System from ETSI EN 302 307-1 V1.4.1 |\n\n## Functional guidelines\n\n* Behaviour should match exactly what GNU Radio produces for every combination of\n  parameters described on the DVB-S2 base spec (no extensions yet). This means\n  components should handle\n  * Frame types: Normal and short\n  * Constellations: 8 PSK, 16 APSK and 32 APSK\n  * Code rates: 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10,\n* Components should also handle parameters changing on every frame, that is, they\n  should handle frame with config A then a frame with config B immediately\n  afterwards without requiring reset or wait cycles\n* Use AXI-Stream interfaces\n\n## Components' status\n\n\u003c!-- Definitions of each development stage: --\u003e\n\n\u003c!-- * Simulation --\u003e\n\u003c!--   * Data must match GNU Radio's output --\u003e\n\u003c!--   * **Back to back data:** check no bubbles are inserted --\u003e\n\u003c!--   * **Slow reader:** check that AXI backpressure works as expected --\u003e\n\u003c!--   * **Slow writer:** check that output data is throttled correctly --\u003e\n\u003c!--   * **Slow write and reader:** check AXI handshaking works as expected --\u003e\n\u003c!-- * Hardware testing --\u003e\n\u003c!--   * Check components is synthesized/implemented as expected by EDA tools --\u003e\n\u003c!--   * Check for possible timing issues (too many logic levels, unintended latches, --\u003e\n\u003c!--     etc) --\u003e\n\u003c!--   [\u003e * Still TBD. Basic idea is to stream data in/out via PCIe or DDR where the host \u003c] --\u003e\n\u003c!--   [\u003e   compares the actual and the expected results \u003c] --\u003e\n\u003c!--   [\u003e * Might be interesting to have a generic GNU Radio to PCIe bridge so that one \u003c] --\u003e\n\u003c!--   [\u003e   could offload create a block diagram on GRC and run parts of it on a real \u003c] --\u003e\n\u003c!--   [\u003e   card \u003c] --\u003e\n\u003c!-- * Hardware integration --\u003e\n\u003c!--   * Same as hardware testing but chaining components together to check it handles --\u003e\n\u003c!--     multiple configs as expected --\u003e\n\u003c!--   * Check that timing constraints are met when components are used together --\u003e\n\n### Core DVB-S2 components\n\n| Component name         | Simulation | HW testing |\n| :---                   | :---:      | :--:       |\n| Baseband scrambler     | ✔          | ✔          |\n| BCH encoder            | ✔          | ✔          |\n| Bit interleaver        | ✔          | ✔          |\n| Constellation mapper   | ✔          | ✔          |\n| LDPC Encoder           | ✔          | ✔          |\n| Physical layer framing | ✔          | ✔          |\n\n### Performance and resource usage (WIP)\n\nThe [dvb_fpga/rtl/dvbs2_encoder.vhd](https://github.com/phase4ground/dvb_fpga/blob/master/rtl/dvbs2_encoder.vhd)\ntop level has been run through Vivado targeting a `xczu4cg-sfvc784-1LV-i` and\nwith a clock frequency of 300 MHz (both arbitrary). No timing issues were\nreported and the resource usage post implementation is show below. Table below\nassumes default values for generics, i.e., `POLYPHASE_FILTER_NUMBER_TAPS` =\n`33`, `POLYPHASE_FILTER_RATE_CHANGE` = `2` and `DATA_WIDTH` = `32`.\n\n| Component                      | LUTs      | FFs       | RAMB   | DSPs   |\n| :---                           | --:       | --:       | --:    | --:    |\n| axi_baseband_scrambler         | 277       | 46        | 0      | 0      |\n| axi_bch_encoder                | 1397      | 1380      | 0      | 0      |\n| axi_ldpc_encoder               | 1017      | 558       | 6      | 0      |\n| axi_bit_interleaver            | 339       | 262       | 10     | 0      |\n| axi_constellation_mapper       | 599       | 253       | 0      | 0      |\n| axi_physical_layer_framer      | 280       | 268       | 0      | 0      |\n| + axi_physical_layer_header    | 13        | 100       | 0      | 0      |\n| + axi_physical_layer_scrambler | 39        | 70        | 0      | 0      |\n| + dummy_frame_generator        | 48        | 21        | 0      | 0      |\n| polyphase_filter_i/q           | 162       | 2168      | 0      | 64     |\n| Register map                   | 586       | 318       | 0      | 0      |\n| Debug infrastructure           | 374       | 581       | 0      | 0      |\n| Others                         | 1470      | 283       | 4      | 0      |\n| **TOTAL**                      | **~6.5k** | **~6.1k** | **20** | **64** |\n\nFor details on what the \"Others\" row includes, see the [DVB-S2 Tx top level block\ndiagram][wiki] in the wiki.\n\n## Running tests\n\nTests can be run locally or on a Docker container. Running locally will require\nGNU Radio, VUnit and a VHDL simulator.\n\n### Using Docker\n\nUses the same container used for CI\n\n```sh\n# Clone this repo and submodules\ngit clone --recurse-submodules  https://github.com/phase4ground/dvb_fpga\ncd dvb_fpga\n# Run the tests\n./misc/run_tests.sh\n```\n\nArguments passed to `docker/run_tests.sh` will be passed to `run.py` and, by\nextension, to VUnit (no environment variable is passed on though). This will\ngenerate gnuradio_data (test data).\n\n### Running locally\n\n* Requirements\n  * GNU Radio\n  * A VHDL simulator\n  * [VUnit][vunit]\n\n```sh\n# Install VUnit\npip install vunit-hdl\n# Clone this repo and submodules\ngit clone --recurse-submodules  https://github.com/phase4ground/dvb_fpga\ncd dvb_fpga\n# Run the tests\n./run.py\n```\n\nThe first invocation of `run.py` will run GNURadio and create stimulus files.\n\nTo list tests use `./run.py -l`:\n\n```sh\n$ ./run.py -l\nlib.axi_bit_interleaver_tb.data_width=8,all_parameters.back_to_back\nlib.axi_bit_interleaver_tb.data_width=8,all_parameters.slow_master\nlib.axi_bit_interleaver_tb.data_width=8,all_parameters.slow_slave\nlib.axi_bit_interleaver_tb.data_width=8,all_parameters.both_slow\nlib.axi_ldpc_table_tb.test_all_configs.back_to_back\nlib.axi_ldpc_table_tb.test_all_configs.slow_master\nlib.axi_ldpc_table_tb.test_all_configs.slow_slave\nlib.axi_ldpc_table_tb.test_all_configs.slow_master,slow_slave\nlib.axi_bch_encoder_tb.test_all_configs.back_to_back\nlib.axi_bch_encoder_tb.test_all_configs.slow_master\nlib.axi_bch_encoder_tb.test_all_configs.slow_slave\nlib.axi_bch_encoder_tb.test_all_configs.both_slow\nlib.dvbs2_encoder_tb.test_all_configs.back_to_back\nlib.axi_ldpc_encoder_core_tb.test_all_configs.back_to_back\nlib.axi_ldpc_encoder_core_tb.test_all_configs.data=0.5,table=1.0,slave=1.0\nlib.axi_ldpc_encoder_core_tb.test_all_configs.data=1.0,table=1.0,slave=0.5\nlib.axi_ldpc_encoder_core_tb.test_all_configs.data=0.75,table=1.0,slave=0.75\nlib.axi_ldpc_encoder_core_tb.test_all_configs.data=1.0,table=0.5,slave=1.0\nlib.axi_ldpc_encoder_core_tb.test_all_configs.data=1.0,table=0.75,slave=0.75\nlib.axi_ldpc_encoder_core_tb.test_all_configs.data=0.8,table=0.8,slave=0.8\nlib.axi_baseband_scrambler_tb.test_all_configs.back_to_back\nlib.axi_baseband_scrambler_tb.test_all_configs.slow_master\nlib.axi_baseband_scrambler_tb.test_all_configs.slow_slave\nlib.axi_baseband_scrambler_tb.test_all_configs.both_slow\nListed 24 tests\n```\n\n## Running synthesis\n\nScripts are provided as an example to get things going, currently this has not\nbeen tested in real hardware.\n\n### Yosys\n\n```sh\n./misc/run_synth.sh\n```\n\n### Vivado\n\n```sh\nvivado -source ./build/vivado/build.tcl\n```\n\n[vunit]: https://vunit.github.io/\n[wiki]: https://github.com/phase4ground/dvb_fpga/wiki#dvb-s2-tx\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FOpenResearchInstitute%2Fdvb_fpga","html_url":"https://awesome.ecosyste.ms/projects/github.com%2FOpenResearchInstitute%2Fdvb_fpga","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FOpenResearchInstitute%2Fdvb_fpga/lists"}