{"id":13633032,"url":"https://github.com/PyHDI/Pyverilog","last_synced_at":"2025-04-18T10:33:50.452Z","repository":{"id":12255326,"uuid":"14871471","full_name":"PyHDI/Pyverilog","owner":"PyHDI","description":"Python-based Hardware Design Processing Toolkit for Verilog HDL","archived":false,"fork":false,"pushed_at":"2024-06-15T15:44:30.000Z","size":718,"stargazers_count":622,"open_issues_count":74,"forks_count":173,"subscribers_count":43,"default_branch":"develop","last_synced_at":"2024-10-07T03:18:54.434Z","etag":null,"topics":["code-generator","compiler","control-flow-analyzer","dataflow-analyzer","hardware","parser","python","verilog-hdl"],"latest_commit_sha":null,"homepage":"","language":"Python","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"apache-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/PyHDI.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2013-12-02T18:53:03.000Z","updated_at":"2024-10-06T09:48:18.000Z","dependencies_parsed_at":"2023-01-13T16:51:26.512Z","dependency_job_id":"c8fa10c2-3b0a-4ece-b766-60dfaa95a8dd","html_url":"https://github.com/PyHDI/Pyverilog","commit_stats":{"total_commits":301,"total_committers":17,"mean_commits":"17.705882352941178","dds":"0.11960132890365449","last_synced_commit":"81838bc463d17148ef6872af34eb27585ee349ba"},"previous_names":[],"tags_count":28,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/PyHDI%2FPyverilog","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/PyHDI%2FPyverilog/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/PyHDI%2FPyverilog/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/PyHDI%2FPyverilog/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/PyHDI","download_url":"https://codeload.github.com/PyHDI/Pyverilog/tar.gz/refs/heads/develop","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":223779401,"owners_count":17201172,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["code-generator","compiler","control-flow-analyzer","dataflow-analyzer","hardware","parser","python","verilog-hdl"],"created_at":"2024-08-01T23:00:25.354Z","updated_at":"2024-11-09T02:30:58.707Z","avatar_url":"https://github.com/PyHDI.png","language":"Python","funding_links":[],"categories":["Verilog-Toolkit","Python","HDL parsers","Circuit Compilers","工具分类"],"sub_categories":["HDL 解析与分析工具"],"readme":"Pyverilog\n==============================\n\n[![CI](https://github.com/PyHDI/Pyverilog/actions/workflows/main.yml/badge.svg)](https://github.com/PyHDI/Pyverilog/actions/workflows/main.yml)\n[![Build Status](https://www.travis-ci.com/PyHDI/Pyverilog.svg?branch=develop)](https://www.travis-ci.com/PyHDI/Pyverilog)\n\nPython-based Hardware Design Processing Toolkit for Verilog HDL\n\nCopyright 2013, Shinya Takamaeda-Yamazaki and Contributors\n\n\nLicense\n==============================\n\nApache License 2.0 (http://www.apache.org/licenses/LICENSE-2.0)\n\n\nPublication\n==============================\n\nIf you use Pyverilog in your research, please cite the following paper.\n\n- Shinya Takamaeda-Yamazaki: Pyverilog: A Python-based Hardware Design Processing Toolkit for Verilog HDL, 11th International Symposium on Applied Reconfigurable Computing (ARC 2015) (Poster), Lecture Notes in Computer Science, Vol.9040/2015, pp.451-460, April 2015.\n[Paper](http://link.springer.com/chapter/10.1007/978-3-319-16214-0_42)\n\n```\n@inproceedings{Takamaeda:2015:ARC:Pyverilog,\ntitle={Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL},\nauthor={Takamaeda-Yamazaki, Shinya},\nbooktitle={Applied Reconfigurable Computing},\nmonth={Apr},\nyear={2015},\npages={451-460},\nvolume={9040},\nseries={Lecture Notes in Computer Science},\npublisher={Springer International Publishing},\ndoi={10.1007/978-3-319-16214-0_42},\nurl={http://dx.doi.org/10.1007/978-3-319-16214-0_42},\n}\n```\n\n\nWhat's Pyverilog?\n==============================\n\nPyverilog is an open-source hardware design processing toolkit for Verilog HDL. All source codes are written in Python.\n\nPyverilog includes **(1) code parser, (2) dataflow analyzer, (3) control-flow analyzer and (4) code generator**.\nYou can create your own design analyzer, code translator and code generator of Verilog HDL based on this toolkit.\n\n\nContribute to Pyverilog\n==============================\n\nPyverilog project always welcomes questions, bug reports, feature proposals, and pull requests on [GitHub](https://github.com/PyHDI/Pyverilog).\n\nfor questions, bug reports, and feature proposals\n--------------------\n\nPlease leave your comment on the [issue tracker](https://github.com/PyHDI/Pyverilog/issues) on GitHub.\n\nfor pull requests\n--------------------\n\nPlease check \"CONTRIBUTORS.md\" for the contributors who provided pull requests.\n\nPyverilog uses **pytest** for the integration testing. **When you send a pull request, please include a testing example with pytest.**\nTo write a testing code, please refer the existing testing examples in \"tests\" directory.\n\nIf the pull request code passes all the tests successfully and has no obvious problem, it will be merged to the *develop* branch by the main committers.\n\n\nInstallation\n==============================\n\nRequirements\n--------------------\n\n- Python3: 3.7 or later\n- Icarus Verilog: 10.1 or later\n\n```\nsudo apt install iverilog\n```\n\n- Jinja2: 2.10 or later\n- PLY: 3.4 or later\n\n```\npip3 install jinja2 ply\n```\n\nOptional installation for testing\n--------------------\n\nThese are required for automatic testing of **tests**.\nWe recommend to install these testing library to verify experimental features.\n\n- pytest: 3.8.1 or later\n- pytest-pythonpath: 0.7.3 or later\n\n```\npip3 install pytest pytest-pythonpath\n```\n\nOptional installation for visualization\n--------------------\n\nThese are required for graph visualization by dataflow/graphgen.py and controlflow/controlflow_analyzer.py.\n\n- Graphviz: 2.38.0 or later\n- Pygraphviz: 1.3.1 or later\n\n```\nsudo apt install graphviz\npip3 install pygraphviz\n```\n\nInstall\n--------------------\n\nNow you can install Pyverilog using setup.py script:\n\n```\npython3 setup.py install\n```\n\n\nTools\n==============================\n\nThis software includes various tools for Verilog HDL design.\n\n* vparser: Code parser to generate AST (Abstract Syntax Tree) from source codes of Verilog HDL.\n* dataflow: Dataflow analyzer with an optimizer to remove redundant expressions and some dataflow handling tools.\n* controlflow: Control-flow analyzer with condition analyzer that identify when a signal is activated.\n* ast\\_code\\_generator: Verilog HDL code generator from AST.\n\n\nGetting Started\n==============================\n\nFirst, please prepare a Verilog HDL source file as below. The file name is 'test.v'.\nThis sample design adds the input value internally whtn the enable signal is asserted. Then is outputs its partial value to the LED.\n\n```verilog\nmodule top\n  (\n   input CLK, \n   input RST,\n   input enable,\n   input [31:0] value,\n   output [7:0] led\n  );\n  reg [31:0] count;\n  reg [7:0] state;\n  assign led = count[23:16];\n  always @(posedge CLK) begin\n    if(RST) begin\n      count \u003c= 0;\n      state \u003c= 0;\n    end else begin\n      if(state == 0) begin\n        if(enable) state \u003c= 1;\n      end else if(state == 1) begin\n        state \u003c= 2;\n      end else if(state == 2) begin\n        count \u003c= count + value;\n        state \u003c= 0;\n      end\n    end\n  end\nendmodule\n```\n\nCode parser\n------------------------------\n\nLet's try syntax analysis. Please type the command as below.\n\n```\npython3 pyverilog/examples/example_parser.py test.v\n```\n\nThen you got the result as below. The result of syntax analysis is displayed.\n\n```\nSource:  (at 1)\n  Description:  (at 1)\n    ModuleDef: top (at 1)\n      Paramlist:  (at 0)\n      Portlist:  (at 2)\n        Ioport:  (at 3)\n          Input: CLK, False (at 3)\n        Ioport:  (at 4)\n          Input: RST, False (at 4)\n        Ioport:  (at 5)\n          Input: enable, False (at 5)\n        Ioport:  (at 6)\n          Input: value, False (at 6)\n            Width:  (at 6)\n              IntConst: 31 (at 6)\n              IntConst: 0 (at 6)\n        Ioport:  (at 7)\n          Output: led, False (at 7)\n            Width:  (at 7)\n              IntConst: 7 (at 7)\n              IntConst: 0 (at 7)\n      Decl:  (at 9)\n        Reg: count, False (at 9)\n          Width:  (at 9)\n            IntConst: 31 (at 9)\n            IntConst: 0 (at 9)\n      Decl:  (at 10)\n        Reg: state, False (at 10)\n          Width:  (at 10)\n            IntConst: 7 (at 10)\n            IntConst: 0 (at 10)\n      Assign:  (at 11)\n        Lvalue:  (at 11)\n          Identifier: led (at 11)\n        Rvalue:  (at 11)\n          Partselect:  (at 11)\n            Identifier: count (at 11)\n            IntConst: 23 (at 11)\n            IntConst: 16 (at 11)\n      Always:  (at 12)\n        SensList:  (at 12)\n          Sens: posedge (at 12)\n            Identifier: CLK (at 12)\n        Block: None (at 12)\n          IfStatement:  (at 13)\n            Identifier: RST (at 13)\n            Block: None (at 13)\n              NonblockingSubstitution:  (at 14)\n                Lvalue:  (at 14)\n                  Identifier: count (at 14)\n                Rvalue:  (at 14)\n                  IntConst: 0 (at 14)\n              NonblockingSubstitution:  (at 15)\n                Lvalue:  (at 15)\n                  Identifier: state (at 15)\n                Rvalue:  (at 15)\n                  IntConst: 0 (at 15)\n            Block: None (at 16)\n              IfStatement:  (at 17)\n                Eq:  (at 17)\n                  Identifier: state (at 17)\n                  IntConst: 0 (at 17)\n                Block: None (at 17)\n                  IfStatement:  (at 18)\n                    Identifier: enable (at 18)\n                    NonblockingSubstitution:  (at 18)\n                      Lvalue:  (at 18)\n                        Identifier: state (at 18)\n                      Rvalue:  (at 18)\n                        IntConst: 1 (at 18)\n                IfStatement:  (at 19)\n                  Eq:  (at 19)\n                    Identifier: state (at 19)\n                    IntConst: 1 (at 19)\n                  Block: None (at 19)\n                    NonblockingSubstitution:  (at 20)\n                      Lvalue:  (at 20)\n                        Identifier: state (at 20)\n                      Rvalue:  (at 20)\n                        IntConst: 2 (at 20)\n                  IfStatement:  (at 21)\n                    Eq:  (at 21)\n                      Identifier: state (at 21)\n                      IntConst: 2 (at 21)\n                    Block: None (at 21)\n                      NonblockingSubstitution:  (at 22)\n                        Lvalue:  (at 22)\n                          Identifier: count (at 22)\n                        Rvalue:  (at 22)\n                          Plus:  (at 22)\n                            Identifier: count (at 22)\n                            Identifier: value (at 22)\n                      NonblockingSubstitution:  (at 23)\n                        Lvalue:  (at 23)\n                          Identifier: state (at 23)\n                        Rvalue:  (at 23)\n                          IntConst: 0 (at 23)\n```\n\nDataflow analyzer\n------------------------------\n\nLet's try dataflow analysis. Please type the command as below.\n\n```\npython3 pyverilog/examples/example_dataflow_analyzer.py -t top test.v \n```\n\nThen you got the result as below. The result of each signal definition and each signal assignment are displayed.\n\n```\nDirective:\nInstance:\n(top, 'top')\nTerm:\n(Term name:top.led type:{'Output'} msb:(IntConst 7) lsb:(IntConst 0))\n(Term name:top.enable type:{'Input'} msb:(IntConst 0) lsb:(IntConst 0))\n(Term name:top.CLK type:{'Input'} msb:(IntConst 0) lsb:(IntConst 0))\n(Term name:top.count type:{'Reg'} msb:(IntConst 31) lsb:(IntConst 0))\n(Term name:top.state type:{'Reg'} msb:(IntConst 7) lsb:(IntConst 0))\n(Term name:top.RST type:{'Input'} msb:(IntConst 0) lsb:(IntConst 0))\n(Term name:top.value type:{'Input'} msb:(IntConst 31) lsb:(IntConst 0))\nBind:\n(Bind dest:top.count tree:(Branch Cond:(Terminal top.RST) True:(IntConst 0) False:(Branch Cond:(Operator Eq Next:(Terminal top.state),(IntConst 0)) False:(Branch Cond:(Operator Eq Next:(Terminal top.state),(IntConst 1)) False:(Branch Cond:(Operator Eq Next:(Terminal top.state),(IntConst 2)) True:(Operator Plus Next:(Terminal top.count),(Terminal top.value)))))))\n(Bind dest:top.state tree:(Branch Cond:(Terminal top.RST) True:(IntConst 0) False:(Branch Cond:(Operator Eq Next:(Terminal top.state),(IntConst 0)) True:(Branch Cond:(Terminal top.enable) True:(IntConst 1)) False:(Branch Cond:(Operator Eq Next:(Terminal top.state),(IntConst 1)) True:(IntConst 2) False:(Branch Cond:(Operator Eq Next:(Terminal top.state),(IntConst 2)) True:(IntConst 0))))))\n(Bind dest:top.led tree:(Partselect Var:(Terminal top.count) MSB:(IntConst 23) LSB:(IntConst 16)))\n```\n\nLet's view the result of dataflow analysis as a picture file. Now we select 'led' as the target. Please type the command as below. In this example, Graphviz and Pygraphviz are installed.\n\n```\npython3 pyverilog/examples/example_graphgen.py -t top -s top.led test.v \n```\n\nThen you got a png file (out.png). The picture shows that the definition of 'led' is a part-selection of 'count' from 23-bit to 16-bit.\n\n![out.png](img/out.png)\n\nControl-flow analyzer\n------------------------------\n\nLet's try control-flow analysis. Please type the command as below. In this example, Graphviz and Pygraphviz are installed. If don't use Graphviz, please append \"--nograph\" option.\n\n```\npython3 pyverilog/examples/example_controlflow_analyzer.py -t top test.v \n```\n\nThen you got the result as below. The result shows that the state machine structure and transition conditions to the next state in the state machine.\n\n```\nFSM signal: top.count, Condition list length: 4\nFSM signal: top.state, Condition list length: 5\nCondition: (Ulnot, Eq), Inferring transition condition\nCondition: (Eq, top.enable), Inferring transition condition\nCondition: (Ulnot, Ulnot, Eq), Inferring transition condition\n# SIGNAL NAME: top.state\n# DELAY CNT: 0\n0 --(top_enable\u003e'd0)--\u003e 1\n1 --None--\u003e 2\n2 --None--\u003e 0\nLoop\n(0, 1, 2)\n```\n\nYou got also a png file (top_state.png), if you did not append \"--nograph\". The picture shows that the graphical structure of the state machine.\n\n![top_state.png](img/top_state.png)\n\nCode generator\n------------------------------\n \nFinally, let's try code generation. Please prepare a Python script as below. The file name is 'test.py'.\nA Verilog HDL code is represented by using the AST classes defined in 'vparser.ast'.\n\n```python\nfrom __future__ import absolute_import\nfrom __future__ import print_function\nimport sys\nimport os\nimport pyverilog.vparser.ast as vast\nfrom pyverilog.ast_code_generator.codegen import ASTCodeGenerator\n\ndef main():\n    datawid = vast.Parameter( 'DATAWID', vast.Rvalue(vast.IntConst('32')) )\n    params = vast.Paramlist( [datawid] )\n    clk = vast.Ioport( vast.Input('CLK') )\n    rst = vast.Ioport( vast.Input('RST') )\n    width = vast.Width( vast.IntConst('7'), vast.IntConst('0') )\n    led = vast.Ioport( vast.Output('led', width=width) )\n    ports = vast.Portlist( [clk, rst, led] )\n\n    width = vast.Width( vast.Minus(vast.Identifier('DATAWID'), vast.IntConst('1')), vast.IntConst('0') )\n    count = vast.Reg('count', width=width)\n\n    assign = vast.Assign(\n        vast.Lvalue(vast.Identifier('led')), \n        vast.Rvalue(\n            vast.Partselect(\n                vast.Identifier('count'), # count\n                vast.Minus(vast.Identifier('DATAWID'), vast.IntConst('1')), # [DATAWID-1:\n                vast.Minus(vast.Identifier('DATAWID'), vast.IntConst('8'))))) # :DATAWID-8]\n\n    sens = vast.Sens(vast.Identifier('CLK'), type='posedge')\n    senslist = vast.SensList([ sens ])\n\n    assign_count_true = vast.NonblockingSubstitution(\n        vast.Lvalue(vast.Identifier('count')),\n        vast.Rvalue(vast.IntConst('0')))\n    if0_true = vast.Block([ assign_count_true ])\n\n    # count + 1\n    count_plus_1 = vast.Plus(vast.Identifier('count'), vast.IntConst('1'))\n    assign_count_false = vast.NonblockingSubstitution(\n        vast.Lvalue(vast.Identifier('count')),\n        vast.Rvalue(count_plus_1))\n    if0_false = vast.Block([ assign_count_false ])\n\n    if0 = vast.IfStatement(vast.Identifier('RST'), if0_true, if0_false)\n    statement = vast.Block([ if0 ])\n\n    always = vast.Always(senslist, statement)\n\n    items = []\n    items.append(count)\n    items.append(assign)\n    items.append(always)\n\n    ast = vast.ModuleDef(\"top\", params, ports, items)\n    \n    codegen = ASTCodeGenerator()\n    rslt = codegen.visit(ast)\n    print(rslt)\n\nif __name__ == '__main__':\n    main()\n```\n\nPlease type the command as below at the same directory with Pyverilog.\n\n```\npython3 test.py\n```\n\nThen Verilog HDL code generated from the AST instances is displayed.\n\n```verilog\nmodule top #\n(\n  parameter DATAWID = 32\n)\n(\n  input CLK,\n  input RST,\n  output [7:0] led\n);\n\n  reg [DATAWID-1:0] count;\n  assign led = count[DATAWID-1:DATAWID-8];\n\n  always @(posedge CLK) begin\n    if(RST) begin\n      count \u003c= 0;\n    end else begin\n      count \u003c= count + 1;\n    end\n  end\n\n\nendmodule\n```\n\n\nRelated Project and Site\n==============================\n\n[Veriloggen](https://github.com/PyHDI/veriloggen)\n- A Mixed-Paradigm Hardware Construction Framework\n\n[NNgen](https://github.com/NNgen/nngen)\n- A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network\n\n[IPgen](https://github.com/PyHDI/ipgen)\n- IP-core package generator for AXI4/Avalon\n\n[PyCoRAM](https://github.com/PyHDI/PyCoRAM)\n- Python-based Portable IP-core Synthesis Framework for FPGA-based Computing\n\n[flipSyrup](https://github.com/shtaxxx/flipSyrup)\n- Cycle-Accurate Hardware Simulation Framework on Abstract FPGA Platforms\n\n[Pyverilog_toolbox](https://github.com/fukatani/Pyverilog_toolbox)\n- Pyverilog_toolbox is Pyverilog-based verification/design tool, which is developed by Fukatani-san and uses Pyverilog as a fundamental library. Thanks for your contribution!\n\n[shtaxxx.hatenablog.com](http://shtaxxx.hatenablog.com/entry/2014/01/01/045856)\n- Blog entry for introduction and examples of Pyverilog (in Japansese)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FPyHDI%2FPyverilog","html_url":"https://awesome.ecosyste.ms/projects/github.com%2FPyHDI%2FPyverilog","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FPyHDI%2FPyverilog/lists"}