{"id":13815841,"url":"https://github.com/Redcrafter/verilog2factorio","last_synced_at":"2025-05-15T09:34:04.850Z","repository":{"id":37260159,"uuid":"350018695","full_name":"Redcrafter/verilog2factorio","owner":"Redcrafter","description":"This project will compile verilog (a hardware description language) into factorio blueprints.","archived":false,"fork":false,"pushed_at":"2025-02-03T01:26:35.000Z","size":6968,"stargazers_count":768,"open_issues_count":0,"forks_count":21,"subscribers_count":8,"default_branch":"main","last_synced_at":"2025-02-03T02:25:28.829Z","etag":null,"topics":["compiler","factorio","verilog"],"latest_commit_sha":null,"homepage":"https://redcrafter.github.io/verilog2factorio/","language":"TypeScript","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"gpl-3.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/Redcrafter.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2021-03-21T14:14:04.000Z","updated_at":"2025-02-03T01:26:39.000Z","dependencies_parsed_at":"2022-09-12T03:41:44.545Z","dependency_job_id":"3823e2a3-6446-4fb5-abf9-26752be77b2d","html_url":"https://github.com/Redcrafter/verilog2factorio","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Redcrafter%2Fverilog2factorio","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Redcrafter%2Fverilog2factorio/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Redcrafter%2Fverilog2factorio/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Redcrafter%2Fverilog2factorio/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/Redcrafter","download_url":"https://codeload.github.com/Redcrafter/verilog2factorio/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":254314198,"owners_count":22050187,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["compiler","factorio","verilog"],"created_at":"2024-08-04T04:04:13.352Z","updated_at":"2025-05-15T09:34:04.844Z","avatar_url":"https://github.com/Redcrafter.png","language":"TypeScript","funding_links":[],"categories":["TypeScript"],"sub_categories":[],"readme":"# Factorio verilog compiler\n\nThis project will compile verilog (a hardware description language) into factorio blueprints.\\\nUsing [this](https://github.com/ghdl/ghdl-yosys-plugin) it should also be possible to compile vhdl. (not tested)\n\n## Web Demo\nYou can check out the web demo [here](https://redcrafter.github.io/verilog2factorio).\n\n## Install\nManually compile [Yosys 0.34](https://github.com/YosysHQ/yosys/releases/tag/yosys-0.34) (later releases might not work) and add it to your PATH.\n\nRun ``` npm install ``` to install all dependencies.\n\n## Usage\n```\nUsage: v2f [options] \u003cfiles..\u003e\n\nOptions:\n  -v, --verbose\n  -d  --debug               Generate debug information. (A graph of the output circuit.)\n  -o, --output \u003cfile\u003e       File to output the compiled blueprint to.\n  -m, --modules \u003cnames...\u003e  Verilog modules to output blueprint for. (defaults to all).\n  -f, --files \u003cfiles...\u003e    List of Verilog files to compile. (only has to be explicitly specified after -m).\n  -g, --generator [type]    Layout generator to use. annealing(default),matrix,chunkAnnealing\n  -h, --help                Display this information.\n```\n## Quick Start\nRun ```./v2f``` with verilog files as parameters. Example: `./v2f ./samples/counter.v`\n\nThe compiled blueprint will be output on the command line unless otherwise specified with `-f`.\n\nThe circuit will have inputs and outputs at the top in the order in which they were written in the code.\nClock pulses are required to be exactly one tick high. (since adding edge detectors would produce a lot of overhead)\n\n## Examples\n\n### samples/counter.v\n```verilog\nmodule counter(input clk, input rst, input inc, output reg [3:0] cnt);\n  always @(posedge clk) begin\n    if (rst)\n      cnt \u003c= 0;\n    else if (inc)\n      cnt \u003c= cnt + 1'b1;\n  end\nendmodule\n```\n![image](https://user-images.githubusercontent.com/35386456/115978416-2c589600-a54d-11eb-8cbd-92d37e0ef3bb.png)\n\nAt the top in order clk, rst, inc and cnt.\n\n### 6502 CPU from https://github.com/Arlet/verilog-6502/\nusing the new layout method \"chunkAnnealing\"\n![image](https://github.com/Redcrafter/verilog2factorio/assets/19157738/c560b2bc-b943-4d40-9aad-64d8d7a33df2)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FRedcrafter%2Fverilog2factorio","html_url":"https://awesome.ecosyste.ms/projects/github.com%2FRedcrafter%2Fverilog2factorio","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FRedcrafter%2Fverilog2factorio/lists"}