{"id":13649357,"url":"https://github.com/RickyTino/MangoMIPS32","last_synced_at":"2025-04-22T14:31:31.668Z","repository":{"id":165405013,"uuid":"153412736","full_name":"RickyTino/MangoMIPS32","owner":"RickyTino","description":"A softcore microprocessor of MIPS32 architecture.","archived":false,"fork":false,"pushed_at":"2024-06-28T17:38:20.000Z","size":428,"stargazers_count":39,"open_issues_count":0,"forks_count":10,"subscribers_count":5,"default_branch":"master","last_synced_at":"2024-11-10T00:33:00.433Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/RickyTino.png","metadata":{"files":{"readme":"README.md","changelog":"ChangeLog.md","contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2018-10-17T07:18:40.000Z","updated_at":"2023-11-30T18:28:19.000Z","dependencies_parsed_at":"2024-01-14T11:00:20.077Z","dependency_job_id":"c5982934-86e5-4869-937e-d8a4ac837ac5","html_url":"https://github.com/RickyTino/MangoMIPS32","commit_stats":null,"previous_names":[],"tags_count":5,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/RickyTino%2FMangoMIPS32","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/RickyTino%2FMangoMIPS32/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/RickyTino%2FMangoMIPS32/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/RickyTino%2FMangoMIPS32/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/RickyTino","download_url":"https://codeload.github.com/RickyTino/MangoMIPS32/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":250258972,"owners_count":21401013,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-02T01:04:57.866Z","updated_at":"2025-04-22T14:31:26.654Z","avatar_url":"https://github.com/RickyTino.png","language":"Verilog","funding_links":[],"categories":["Verilog"],"sub_categories":[],"readme":"# MangoMIPS32\nMangoMIPS32 is a soft-core microprocessor written in Verilog HDL. It is compliant to MIPS32 release 1 architecture.\n\n## Current Version\nMangoMIPS32 v1.1.3  \nThis version succeded running Linux 2.6.32\n\n## CPU Core \n- Supports 100 instructions in MIPS32r1 ISA (Listed below)\n- Single-issued 5-stage pipeline structure\n- Speed: 100MHz on -2 level Xilinx XC7A200T FPGA Chip\n- No floating point units\n\n## Interface and Caches\n- Implemented AMBA-AXI as on-chip bus interface\n- Instruction cache and data cache build with Xilinx Distributed Ram IP Core \n- Write-back, write-allocate, direct-mapped caches\n- size-configurable (2KB-128KB)\n\n## Privilege Resources\n- Implemented 20 coprocessor 0 (CP0) registers\n- Support user mode (could be disabled with macros)\n- Avoided all CP0 Execution Hazards\n\n## Address Mapping\n- Supports both Fixed-mapping MMU and TLB-based MMU\n- 32-items full-associative TLB\n- Support multiple page sizes starting from 4KB\n\n## Details\nInstructions supported:\n- SLL/SRL/SRA/SLLV/SRLV/SRAV\n- SYNC/PREF (Decode as NOP)\n- AND/OR/XOR/NOR\n- MOVZ/MOVN/MFHI/MFLO/MTHI/MTLO\n- ANDI/ORI/XORI/LUI\n- ADD/ADDU/SUB/SUBU/SLT/SLTU/CLO/CLZ\n- ADDI/ADDIU/SLTI/SLTIU\n- MUL/MULT/MULTU/MADD/MADDU/MSUB/MSUBU/DIV/DIVU\n- J/JAL/JR/JALR\n- BEQ/BNE/BGTZ/BLEZ/BGEZ/BGEZAL/BLTZ/BLTZAL\n- BEQL/BNEL/BGTZL/BLEZL/BGEZL/BGEZALL/BLTZL/BLTZALL\n- LB/LBU/LH/LHU/LW/LWL/LWR/LL\n- SB/SH/SW/SWL/SWR/SC\n- MFC0/MTC0\n- SYSCALL/BREAK/ERET/WAIT\n- TEQ/TNE/TGE/TGEU/TLT/TLTU\n- TEQI/TNEI/TGEI/TGEIU/TLTI/TLTIU\n- TLBP/TLBWI/TLBWR/TLBR\n- CACHE:  \n  - I-Index Invalidate  \n  - D-Index Writeback Invalidate  \n  - I-Index Store Tag  \n  - D-Index Store Tag  \n  - I-Hit Invalidate  \n  - D-Hit Invalidate  \n  - D-Hit Writeback Invalidate  \n\nCP0 Registers：  \n\n|   Name   |Reg#|Sel#|  \n|:---------|:--:|:--:|  \n| Index    | 0  | 0  |\n| Random   | 1  | 0  |\n| EntryLo0 | 2  | 0  |\n| EntryLo1 | 3  | 0  |\n| Context  | 4  | 0  |\n| PageMask | 5  | 0  |\n| Wired    | 6  | 0  |\n| BadVAddr | 8  | 0  |\n| Count    | 9  | 0  |\n| EntryHi  | 10 | 0  |\n| Compare  | 11 | 0  |\n| Status   | 12 | 0  |\n| Cause    | 13 | 0  |\n| EPC      | 14 | 0  |\n| PrId     | 15 | 0  |\n| Config   | 16 | 0  |\n| Config1  | 16 | 1  |\n| TagLo    | 28 | 0  |\n| TagHi    | 29 | 0  |\n| ErrorEPC | 30 | 0  |\n\nExceptions (priority ranking)：\n- Reset\n- Interrupt\n- I-Address Error\n- I-TLB Refill\n- I-TLB Invalid\n- Coprocessor Unusable\n- Reserved Instruction\n- Overflow / Trap / Syscall / Breakpoint\n- D-Address Error\n- D-TLB Refill\n- D-TLB Invalid\n- D-TLB Modified\n- ERET\n\n## Related Work\nMangoMIPS32 has an AXI master interface and can fit in these designs:\n- [NSCSCC](http://www.nscscc.org/) Environments\n- [HypoSoC_IoT](https://github.com/hitwh-nscscc/hyposoc_iot)\n- [CatnipSoC](https://github.com/RickyTino/CatnipSoC)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FRickyTino%2FMangoMIPS32","html_url":"https://awesome.ecosyste.ms/projects/github.com%2FRickyTino%2FMangoMIPS32","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FRickyTino%2FMangoMIPS32/lists"}