{"id":13838309,"url":"https://github.com/RipperJ/RISC-V_CPU","last_synced_at":"2025-07-10T21:32:22.586Z","repository":{"id":172426784,"uuid":"347245199","full_name":"RipperJ/RISC-V_CPU","owner":"RipperJ","description":"RISC-V 32i Pipeline CPU and Assembler","archived":false,"fork":false,"pushed_at":"2022-05-06T12:48:42.000Z","size":609,"stargazers_count":17,"open_issues_count":1,"forks_count":3,"subscribers_count":2,"default_branch":"main","last_synced_at":"2024-08-05T15:07:19.757Z","etag":null,"topics":["assembler","cpu","fpga","pipeline-cpu","risc-v","simulation","verilog"],"latest_commit_sha":null,"homepage":"","language":"Python","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/RipperJ.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null}},"created_at":"2021-03-13T01:42:13.000Z","updated_at":"2024-07-29T02:50:24.000Z","dependencies_parsed_at":null,"dependency_job_id":"ad0ed6f9-5111-4a23-a34a-c4282fc0adcb","html_url":"https://github.com/RipperJ/RISC-V_CPU","commit_stats":null,"previous_names":["ripperj/risc-v_cpu"],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/RipperJ%2FRISC-V_CPU","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/RipperJ%2FRISC-V_CPU/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/RipperJ%2FRISC-V_CPU/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/RipperJ%2FRISC-V_CPU/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/RipperJ","download_url":"https://codeload.github.com/RipperJ/RISC-V_CPU/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":225657357,"owners_count":17503548,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["assembler","cpu","fpga","pipeline-cpu","risc-v","simulation","verilog"],"created_at":"2024-08-04T15:01:49.811Z","updated_at":"2024-11-21T01:30:51.581Z","avatar_url":"https://github.com/RipperJ.png","language":"Python","funding_links":[],"categories":["Python"],"sub_categories":[],"readme":"# RISC-V 32i CPU and Assembler\n\nThis is one of the course project materials for HKUST ELEC-5140 **Advanced Computer Architecture**, where students are encouraged to enhance the structural model and improve its performance. This project is alive, maintained by [linfeng.du@connect.ust.hk](linfeng.du@connect.ust.hk). Any discussion or suggestion would be greatly appreciated! \n\n***\n\n## Project Tree\n\n1. **[RV32i](https://github.com/RipperJ/RISC-V_CPU/tree/main/RV32i)** directory contains a Vivado project of RISC-V CPU written in verilog, which implements a 5-stage single-issue processor, supporting 31 basic instructions from [RV32I base instruction set](https://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf#page=148).\n\n2. **[RISC-V_Assembler](https://github.com/RipperJ/RISC-V_CPU/tree/main/RISC-V_Assembler)** directory contains an assembler to translate RISC-V instruction assembly into hexadecimal format, which could be easily directly loaded to instruction memory through `$readmemh` during Vivado simulation.\n\n3. **[tests](https://github.com/RipperJ/RISC-V_CPU/tree/main/tests)** directory contains benchmark written in RV32i assembly. Vec_Mul is a basic coding example.\n\n***\n\n## Assembly Manual\n### What this assembler supports:\n* R-type:\n```\nadd s1, t1, t2 # s1 = t1 + t2\n```\n* I-type:\n```\nslti s1, t1, 3 # if t1 \u003c 3: s1 = 1; else: s1 = 0;\n```\n* Load / Store:\n```\nlw s1, 4(t1) # s1 = *(t1 + 1) // 4 means 4 bytes == 1 word (int size)\nsw s1, 4(t1)\n```\n* Branch:\n```\n# Using immediate value for address is OK\nbeq t1, t2, 0x1000\n# A more convenient way is using labels, like:\n\nThis_Is_A_Label:\n# ... \n# ... do whatever you want\n# ...\nbeq t1, t2, This_Is_A_Label // if t1 == t2, then jump to the first instruction after label \"This_Is_A_Label\"\n```\n* LUI / AUIPC:\n```\nlui x2, 0x12345     # x2 = 0x12345000\naddi x2, x2, 0x678  # x2 = 0x12345678\nauipc x3, 0x0100    # x3 = 0x00100000 + PC\n```\n* JAL / JALR:\n```\njal x1, SOME_LABEL # or some immediate value as address\njalr x0, x1, 0 # only immediate value is allowed for the third parameter!\n               # by the way, this is equal to \"jr ra\" in its effect\n               # you can realize calling a function with \"jal\" and \"jalr\"\n```\n* comments:\n```\n# This is a line of comment\n// This is also a line of comment\nadd s1, s2, s3 # This is a line of comment following one instruction\nadd s1, s2, s3 // This is also a line of comment following one instruction\n```\n* Others\n```\n# 1. Case Insensitivity\nadd s1, t1, t2 // OK\nADD s2, t1, t1 // also OK\n# 2. Supporting both Register Name and ABI Name\n// Instead of using register name 'x0', 'x1', you can also use 'zero', 'ra',\n// which makes your assembly more readable\n```\n\n***\n\n## TODO\n* Assembler\n    * [Pseudo Ops](https://github.com/riscv/riscv-asm-manual/blob/master/riscv-asm.md#pseudo-ops)\n    * [Pseudo Instructions](https://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf#page=157)\n    * Make it good-looking...\n\n* CPU\n    * To support other basic instructions\n        * LB, LH, LBU, LHU\n        * SB, SH\n        * FENCE, FENCE.I\n        * ECALL, EBREAK\n        * CSRR*\n\n***\n\n## Reference Link for students\n* [The RISC-V Instruction Set Manual](https://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf)\n    * [RV32i Registers](https://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf#page=155): only x0 ~ x31 are used here.\n    * [RV32I base instruction set](https://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf#page=148)\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FRipperJ%2FRISC-V_CPU","html_url":"https://awesome.ecosyste.ms/projects/github.com%2FRipperJ%2FRISC-V_CPU","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FRipperJ%2FRISC-V_CPU/lists"}