{"id":13626662,"url":"https://github.com/Ronsor/riscv-zig","last_synced_at":"2025-04-16T15:31:25.923Z","repository":{"id":82422208,"uuid":"345868615","full_name":"Ronsor/riscv-zig","owner":"Ronsor","description":"A RISC-V emulator written in Zig","archived":false,"fork":false,"pushed_at":"2021-06-12T01:15:00.000Z","size":11,"stargazers_count":46,"open_issues_count":0,"forks_count":1,"subscribers_count":3,"default_branch":"master","last_synced_at":"2024-08-02T22:27:35.464Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Zig","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/Ronsor.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null}},"created_at":"2021-03-09T03:15:18.000Z","updated_at":"2024-07-27T18:07:42.000Z","dependencies_parsed_at":"2023-06-15T15:15:17.518Z","dependency_job_id":null,"html_url":"https://github.com/Ronsor/riscv-zig","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Ronsor%2Friscv-zig","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Ronsor%2Friscv-zig/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Ronsor%2Friscv-zig/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/Ronsor%2Friscv-zig/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/Ronsor","download_url":"https://codeload.github.com/Ronsor/riscv-zig/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":223716663,"owners_count":17191086,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-01T21:02:25.865Z","updated_at":"2024-11-08T16:31:16.942Z","avatar_url":"https://github.com/Ronsor.png","language":"Zig","readme":"# RV64IM emulator\n\nThis repository contains a library for emulating RISC-V 64 CPUs with the multiply extension.\n\n*Caveat emptor:* The implementation of RISC-V contained herein has not been tested for compliance.\nIt may produce incorrect results, and it most certainly does not reject all invalid instructions.\n\n(C) 2021 Ronsor Labs.\n\n## TODO\n\n* Support RV32 too (should be easy)\n* Implemented privileged instructions\n* Better documentation\n","funding_links":[],"categories":["Zig","Applications","Systems Programming"],"sub_categories":["Emulators"],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FRonsor%2Friscv-zig","html_url":"https://awesome.ecosyste.ms/projects/github.com%2FRonsor%2Friscv-zig","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FRonsor%2Friscv-zig/lists"}