{"id":25653013,"url":"https://github.com/SarwanShah/RISC-V-Architecture-Verilog-Simulation-2021","last_synced_at":"2026-06-30T07:30:17.436Z","repository":{"id":276544763,"uuid":"929585998","full_name":"SarwanShah/HU_2021_RISC-V-Architecture-Verilog","owner":"SarwanShah","description":"In this project we implemented the RISC V processor architecture in Verilog. ","archived":false,"fork":false,"pushed_at":"2025-02-10T00:38:43.000Z","size":11,"stargazers_count":1,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-02-10T01:27:16.249Z","etag":null,"topics":["computer-architecture","processor-design","risc-v","verilog"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/SarwanShah.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2025-02-08T22:16:28.000Z","updated_at":"2025-02-10T00:38:46.000Z","dependencies_parsed_at":"2025-02-10T01:27:17.138Z","dependency_job_id":null,"html_url":"https://github.com/SarwanShah/HU_2021_RISC-V-Architecture-Verilog","commit_stats":null,"previous_names":["sarwanshah/hu_2021_risc_v_architecture_verilog","sarwanshah/hu_2021_risc-v-architecture-verilog"],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/SarwanShah%2FHU_2021_RISC-V-Architecture-Verilog","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/SarwanShah%2FHU_2021_RISC-V-Architecture-Verilog/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/SarwanShah%2FHU_2021_RISC-V-Architecture-Verilog/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/SarwanShah%2FHU_2021_RISC-V-Architecture-Verilog/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/SarwanShah","download_url":"https://codeload.github.com/SarwanShah/HU_2021_RISC-V-Architecture-Verilog/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":240364680,"owners_count":19789802,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["computer-architecture","processor-design","risc-v","verilog"],"created_at":"2025-02-23T19:19:15.546Z","updated_at":"2026-06-30T07:30:17.368Z","avatar_url":"https://github.com/SarwanShah.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# Implementing RISC-V Architecture in Verilog\n\nThis project was developed under the EE-371 Computer Architecture course at Habib University during Spring 2021. This project involves the implementation of a **RISC-V processor architecture** using **Verilog** hardware description language. The RISC-V architecture is a free and open ISA enabling a new era of processor innovation through open standard collaboration.\n\n## Project Features\n\n- **Processor Core Design**: Implementation of the RISC-V processor core in Verilog.\n- **Modular Design**: Organized code structure for different components of the processor.\n- **Simulation Support**: Testbenches for simulating and verifying processor functionality.\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FSarwanShah%2FRISC-V-Architecture-Verilog-Simulation-2021","html_url":"https://awesome.ecosyste.ms/projects/github.com%2FSarwanShah%2FRISC-V-Architecture-Verilog-Simulation-2021","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FSarwanShah%2FRISC-V-Architecture-Verilog-Simulation-2021/lists"}