{"id":13648862,"url":"https://github.com/SpinalHDL/SaxonSoc","last_synced_at":"2025-04-22T11:33:23.987Z","repository":{"id":36503819,"uuid":"159960289","full_name":"SpinalHDL/SaxonSoc","owner":"SpinalHDL","description":"SoC based on VexRiscv and ICE40 UP5K","archived":false,"fork":false,"pushed_at":"2025-03-16T22:00:53.000Z","size":2072,"stargazers_count":155,"open_issues_count":15,"forks_count":41,"subscribers_count":22,"default_branch":"dev-0.3","last_synced_at":"2025-04-05T15:35:33.723Z","etag":null,"topics":["riscv","rtl","soc"],"latest_commit_sha":null,"homepage":null,"language":"Scala","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/SpinalHDL.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2018-12-01T15:49:01.000Z","updated_at":"2025-03-25T05:51:20.000Z","dependencies_parsed_at":"2023-01-17T02:15:31.451Z","dependency_job_id":"5a355a4a-70fb-4e0a-abd2-2870439ad227","html_url":"https://github.com/SpinalHDL/SaxonSoc","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/SpinalHDL%2FSaxonSoc","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/SpinalHDL%2FSaxonSoc/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/SpinalHDL%2FSaxonSoc/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/SpinalHDL%2FSaxonSoc/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/SpinalHDL","download_url":"https://codeload.github.com/SpinalHDL/SaxonSoc/tar.gz/refs/heads/dev-0.3","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":250232582,"owners_count":21396664,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["riscv","rtl","soc"],"created_at":"2024-08-02T01:04:36.757Z","updated_at":"2025-04-22T11:33:23.952Z","avatar_url":"https://github.com/SpinalHDL.png","language":"Scala","funding_links":[],"categories":["Scala","SoC"],"sub_categories":[],"readme":"## Description\n\nThis repo experiment multiple things at once :\n- The BMB (Banana Memory Bus) which can cover both cached and cacheless SoC without compromises\n- A hardware description paradigm made of generators and depedancies which should be able to solve SoC toplevel hell\n- Linux and U-Boot on VexRiscv\n\nA few kits are supported :\n- ulx3s (ECP5) , documented in bsp/radiona/ulx3s/smp/README.md\n- Arty-A7 (Artix 7), documented in bsp/digilent/ArtyA7SmpLinux/README.md\n- [Efinix Xyloni](./hardware/scala/saxon/board/efinix/xyloni/readme.md)   ![xyloni_1](https://user-images.githubusercontent.com/26599790/172013963-737f0f52-707d-4ab9-9b78-31ec360a097c.jpg)\n\n- ...\n\n\n## Repository structure\n\n```\n- hardware\n  - scala      : SpinalHDL hardware description\n  - netlist    : Folder used by SpinalHDL to generate the netlist\n  - synthesis  : Contains synthesis scripts for various boards\n- bsp          : Contains multiple Board Support Package used to build the software\n- software\n  - standalone : Contains multiple demo software to run in the CPU\n- ext\n  - SpinalHDL  : Hardware description language compiler\n  - VexRiscv   : CPU hardware description\n```\n\n## Dependencies\n\nOn Ubuntu 14 :\n\n```sh\n# JAVA JDK \u003e= 8\nsudo add-apt-repository -y ppa:openjdk-r/ppa\nsudo apt-get update\nsudo apt-get install openjdk-8-jdk -y\nsudo update-alternatives --config java\nsudo update-alternatives --config javac\n\n# Install SBT - https://www.scala-sbt.org/\necho \"deb https://repo.scala-sbt.org/scalasbt/debian all main\" | sudo tee /etc/apt/sources.list.d/sbt.list\necho \"deb https://repo.scala-sbt.org/scalasbt/debian /\" | sudo tee /etc/apt/sources.list.d/sbt_old.list\ncurl -sL \"https://keyserver.ubuntu.com/pks/lookup?op=get\u0026search=0x2EE0EA64E40A89B84B2DF73499E82A75642AC823\" | sudo apt-key add\nsudo apt-get update\nsudo apt-get install sbt\n\n# Verilator (for simulation only, v3.9+, in general apt-get will give you 3.8)\nsudo apt-get install git make autoconf g++ flex bison -y  # First time prerequisites\ngit clone http://git.veripool.org/git/verilator   # Only first time\nunsetenv VERILATOR_ROOT  # For csh; ignore error if on bash\nunset VERILATOR_ROOT  # For bash\ncd verilator\ngit pull        # Make sure we're up-to-date\ngit checkout v4.040\nautoconf        # Create ./configure script\n./configure\nmake -j$(nproc)\nsudo make install\necho \"DONE\"\n\n# A fiew dependencies ?\nsudo apt install pkg-config shtool libtool cpio bc unzip rsync mercurial\nsudo apt install libusb-1.0-0-dev libyaml-dev\n```\n\n## Jar package\n\nTo package the project into a dependence free jar : \n\n```\nsbt clean assembly\n```\n\nThe produced jar will be in `target/scala-2.11/SaxonSoc-assembly-1.0.0.jar`\n\nTo run that jar : \n\n```\njava -cp target/scala-2.11/SaxonSoc-assembly-1.0.0.jar YOUR_SCALA_PACKAGE.YOUR_MAIN\n```\n\n## BMB spec (WIP)\n\n### Why BMB\n\nThe needs I had :\n\n- A memory bus which could be used from for cacheless + low latency to cachefull SoC design without overhead\n- Interconnect/Adapters which fit well in FPGA (without asyncronus ram reads)\n\nWhy not adopting a existing memory bus :\n\n- AXI4 memory ordering has overhead for cacheless CPU designs\n- AXI4 do not fit cacheless design as the AW W channels split add overhead to the interconnect\n- Nor AXI4, Wishbone, Avalon provide the features required for state-less adapters\n- With the SaxonSoc out of order elaboration, there was a quite some room for experimentation and automation\n\nNote that Tilelink isn't that bad after all. It has some quite interresting properties and avoid all the AXI bloat. While its out of order nature can seems challenging, it relax a lot of otherwise hard to implement things in the interconnect / L2 caches / memory slaves.\n\n### Key features\n\nFeature which target the interconnect and adapters :\n\n- Context signals which allow a master to retrieve information from the bus responses, and consequently allow state-less adapters\n- State-less adapters allow unlimited number of pending transactions and avoid the usage of RAM/FIFO in adapters\n- Address and write data are part of the same link, which allow to have low latency interconnect (in comparison to AXI)\n- Allow out of oder completion via the 'source' signals\n\nFeature to make slave implementation easier :\n\n- Address alignment parameter (BYTE, WORD, POW2) to allow simple slave implementations\n- Length width parameter, which combined with the alignement parameter, allow a slave to not support bursts (the interconnect will add the required adapters)\n\nOther features :\n\n- WriteOnly, readOnly support\n\n### Signal\n\nBMB is composed of streams to carry transaction between a source and a sink. A stream is composed of :\n\n| Name    | Direction      | Description                                                                  |\n| ------- | -------------- | ---------------------------------------------------------------------------- |\n| valid   | Source =\u003e Sink | transaction present on the interface                                         |\n| payload | Source =\u003e Sink | transaction content                                                          |\n| ready   | Source \u003c= Sink | consume the transaction on the bus, don't care if there is no transaction    |\n\nMore details on [https://spinalhdl.github.io/SpinalDoc-RTD/SpinalHDL/Libraries/stream.html](https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Libraries/stream.html)\n\nBMB is composed of two mandatory streams :\n- cmd : M-\u003eS, to carry requests, (read, write + data)\n- rsp : M\u003c-S, to carry responses (read + data, write)\n\nand three optional streams to handle memory coherency : \n- inv  : M\u003c-S, for the interconnect to ask a master to invalidate a portion of memory\n- ack  : M-\u003eS, for the master to notify the interconnect that an invalidation is now effective\n- sync : M\u003c-S, for the interconnect to notify a master which issued a write that the given write is now observable by all other masters\n\nThe cmd stream is consquantly composed of the following signals\n\n| Name    | Bitcount     | Description                                                                                         |\n| ------- | ------------ | ------------                                                                                        |\n| valid   | 1            | Stream valid                                                                                        |\n| ready   | 1            | Stream ready                                                                                        |\n| source  | sourceWidth  | Transaction source ID, allow out of order completion between different sources, similar to AXI ID   |\n| opcode  | 1            | 0 =\u003e READ, 1 =\u003e WRITE                                                                               |\n| address | addressWidth | Address of the first byte of the transaction, stay the same during a burst                          |\n| length  | lengthWidth  | Burst bytes count - 1                                                                               |\n| data    | dataWidth    | Data used for writes                                                                                |\n| mask    | dataWidth/8  | Data mask used for writes                                                                           |\n| context | contextWidth | Can be used by a master/adapter to link some informations to a burst (returned on rsp transactions) |\n\nDuring a write burst the source, opcode, address, length and context signal should remain stable.\n\nThe rsp stream is :\n\n| Name    | Bitcount     | Description                                |\n| ------- | ------------ | ------------                               |\n| valid   | 1            | Stream valid                               |\n| ready   | 1            | Stream ready                               |\n| source  | sourceWidth  | Identical to the corresponding cmd source  |\n| opcode  | 1            | 0 =\u003e SUCCESS, 1 =\u003e ERROR                   |\n| data    | dataWidth    | Data used for reads                        |\n| context | contextWidth | Identical to the corresponding cmd context |\n\nDuring a read burst the source and context signal should remain stable.\n\nThe inv stream is : \n\n| Name    | Bitcount     | Description                                |\n| ------- | ------------ | ------------                               |\n| valid   | 1            | Stream valid                               |\n| ready   | 1            | Stream ready                               |\n| all     | 1            | 0 =\u003e all masters, 1 =\u003e all masters but the source one should be invalidated. |\n| address | addressWidth | Address of the first byte to invalidate    |\n| length  | lengthWidth  | How many bytes should be invalidated - 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