{"id":13648849,"url":"https://github.com/SpinalHDL/VexiiRiscv","last_synced_at":"2025-04-22T11:33:20.152Z","repository":{"id":206974956,"uuid":"718055281","full_name":"SpinalHDL/VexiiRiscv","owner":"SpinalHDL","description":"Like VexRiscv, but, Harder, Better, Faster, Stronger","archived":false,"fork":false,"pushed_at":"2025-04-15T07:02:06.000Z","size":4120,"stargazers_count":150,"open_issues_count":5,"forks_count":17,"subscribers_count":12,"default_branch":"dev","last_synced_at":"2025-04-15T07:41:25.410Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"","language":"Scala","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/SpinalHDL.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2023-11-13T09:29:53.000Z","updated_at":"2025-04-15T06:59:15.000Z","dependencies_parsed_at":"2024-04-23T12:13:52.967Z","dependency_job_id":"29ffe87c-2e2d-457d-9201-9521bea206de","html_url":"https://github.com/SpinalHDL/VexiiRiscv","commit_stats":null,"previous_names":["spinalhdl/vexiiriscv"],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/SpinalHDL%2FVexiiRiscv","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/SpinalHDL%2FVexiiRiscv/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/SpinalHDL%2FVexiiRiscv/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/SpinalHDL%2FVexiiRiscv/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/SpinalHDL","download_url":"https://codeload.github.com/SpinalHDL/VexiiRiscv/tar.gz/refs/heads/dev","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":250232551,"owners_count":21396661,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-02T01:04:36.368Z","updated_at":"2025-04-22T11:33:20.126Z","avatar_url":"https://github.com/SpinalHDL.png","language":"Scala","funding_links":[],"categories":["Scala","CPU"],"sub_categories":[],"readme":"# VexiiRiscv\n\nVexiiRiscv (Vex2Risc5) is the successor of VexRiscv. Work in progress, here are its currently implemented features :\n\n- RV32/64 I[M][A][F][D][C][S][U][B]\n- Up to 5.24 coremark/Mhz 2.50 dhystone/Mhz\n- In-order execution\n- early [late-alu]\n- single/dual issue (can be asymmetric)\n- BTB, GShare, RAS branch prediction\n- cacheless fetch/load/store\n- Optional I$, D$\n- Optional SV32/SV39 MMU\n- Can run linux / buildroot / Debian\n- Pipeline visualisation in simulation via Konata\n- Lock step simulation via RVLS and Spike\n- AXI4, Wishbone, Tilelink memory busses (RVA is not available in some configs, see the RTD doc SoC main page)\n- ... and many other things\n\nHere is a demonstration of a quad core VexiiRiscv running debian on FPGA : https://youtu.be/dR_jqS13D2c?t=112\n\nOverall the goal is to have a design which can stretch (through configuration) from Cortex M0 up to a Cortex A53 and potentialy beyond.\n\nHere is the online documentation : \n\n- https://spinalhdl.github.io/VexiiRiscv-RTD/master/VexiiRiscv/Introduction/#\n- https://spinalhdl.github.io/VexiiRiscv-RTD/master/VexiiRiscv/HowToUse/index.html\n\nHere is the VexiiRiscv's scala doc (auto-generated from the source code) :\n\n- https://spinalhdl.github.io/VexiiRiscv/doc/vexiiriscv/index.html\n\nA roadmap is available here : \n\n- https://github.com/SpinalHDL/VexiiRiscv/issues/1\n\n# TL;DR Getting started\n\nThe quickest way for getting started is to pull the Docker image with all the dependencies installed\n\nPlease refer to the self contained tutorial for a comprehensive step by step instruction manual with\nscreenshots: https://spinalhdl.github.io/VexiiRiscv-RTD/master/VexiiRiscv/Tutorial/index.html\n\nAfter running the generation you'll find a file named \"VexiiRiscv.v\" in the root\nof the repository folder, which you can drag into your Quartus or whatever.\n\nWe decided to not start covering FPGA boards because there's just too many, so it's up to you\nto define your pin configuration for your specific FPGA board\n\nIf you want to know what else you can do with sbt, please refer to the complete documentation.\n\n# Rebuild the Docker container\n\nIn case you wanna rebuild leviathan's Docker container you can run\n\n    docker build . -f docker/Dockerfile -t vexiiriscv --progress=plain\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FSpinalHDL%2FVexiiRiscv","html_url":"https://awesome.ecosyste.ms/projects/github.com%2FSpinalHDL%2FVexiiRiscv","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FSpinalHDL%2FVexiiRiscv/lists"}