{"id":13648871,"url":"https://github.com/THU-DSP-LAB/ventus-gpgpu","last_synced_at":"2025-04-22T11:33:29.974Z","repository":{"id":58779685,"uuid":"522449414","full_name":"THU-DSP-LAB/ventus-gpgpu","owner":"THU-DSP-LAB","description":"GPGPU processor supporting RISCV-V extension, developed with Chisel HDL","archived":false,"fork":false,"pushed_at":"2025-04-12T13:37:31.000Z","size":35541,"stargazers_count":721,"open_issues_count":3,"forks_count":89,"subscribers_count":14,"default_branch":"master","last_synced_at":"2025-04-12T14:41:48.790Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Scala","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mulanpsl-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/THU-DSP-LAB.png","metadata":{"files":{"readme":"README.md","changelog":"CHANGELOG.md","contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":".github/CODEOWNERS","security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2022-08-08T07:34:22.000Z","updated_at":"2025-04-10T08:23:24.000Z","dependencies_parsed_at":"2023-09-26T12:45:15.052Z","dependency_job_id":"9456e9d2-7b48-4ebb-a421-877abd277f97","html_url":"https://github.com/THU-DSP-LAB/ventus-gpgpu","commit_stats":null,"previous_names":[],"tags_count":1,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/THU-DSP-LAB%2Fventus-gpgpu","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/THU-DSP-LAB%2Fventus-gpgpu/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/THU-DSP-LAB%2Fventus-gpgpu/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/THU-DSP-LAB%2Fventus-gpgpu/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/THU-DSP-LAB","download_url":"https://codeload.github.com/THU-DSP-LAB/ventus-gpgpu/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":250232588,"owners_count":21396665,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-02T01:04:37.020Z","updated_at":"2025-04-22T11:33:24.926Z","avatar_url":"https://github.com/THU-DSP-LAB.png","language":"Scala","funding_links":[],"categories":["Scala","Applications"],"sub_categories":[],"readme":"# Ventus(乘影) GPGPU\nGPGPU processor supporting RISCV-V extension, developed with Chisel HDL.\n\nCopyright 2021-2023 by International Innovation Center of Tsinghua University, Shanghai\n\nWe are calling for contributors. If you are interested in Ventus GPGPU, please contact yff22@mails.tsinghua.edu.cn\n\n“乘影”在RVV编译器工具链、验证环境开发和硬件设计方面还有很多不足，如果您有意愿参与到“乘影”的开发中，欢迎在github上pull request，也欢迎联系 yff22@mails.tsinghua.edu.cn\n\n乘影2.0架构文档在[这里](https://github.com/THU-DSP-LAB/ventus-gpgpu/blob/master/docs/乘影GPGPU架构文档手册v2.0.pdf)，添加了对OpenCL支持所需的改动。如果您在软硬件方面有任何建议，欢迎提issue或邮件联系。\n\n乘影开源GPGPU项目网站：[opengpgpu.org.cn](https://opengpgpu.org.cn/)\n\nHome page of Ventus-GPGPU project: [opengpgpu.org.cn](https://opengpgpu.org.cn/)\n\n乘影软件工具链release版本在[这里](https://opengpgpu.org.cn/html/web/project/release/index.html)获取.\n\nYou can get the release version of software toolchain [here](https://opengpgpu.org.cn/html/web/project/release/index.html).\n\n## Architecture\n\nThe micro-architecture overview of Ventus(乘影) is shown below. \n\nISA and micro-architecture docs is [here](https://github.com/THU-DSP-LAB/ventus-gpgpu/blob/master/docs/ventus%20GPGPU%20architecture%20whitepaper%20v2.0.pdf). Chinese docs is [here](https://github.com/THU-DSP-LAB/ventus-gpgpu/blob/master/docs/乘影GPGPU架构文档手册v2.0.pdf). \n\nOpenCL C compiler based on LLVM is developed by Terapines([兆松科技](https://www.terapines.com/)).\n\nUse the script in [ventus-llvm](https://github.com/THU-DSP-LAB/llvm-project) to configure the complete software toolchain, including [isa-simulator](https://github.com/THU-DSP-LAB/ventus-gpgpu-isa-simulator), [pocl](https://github.com/THU-DSP-LAB/pocl) and [driver](https://github.com/THU-DSP-LAB/pocl).\n\n\n![](./docs/images/ventus_arch.png)\n\n## Quick Start\n[从零开始的配置教程](https://zhuanlan.zhihu.com/p/586445036)（中文，从WSL和IDEA安装讲起）\n\nThe tutorial of Chisel development environment configuration comes from [chipsalliance/playground: chipyard in mill :P](https://github.com/chipsalliance/playground)\n\n0. Install dependencies and setup environments: \n- Arch Linux  \n`pacman -Syu --noconfirm make parallel wget cmake ninja mill dtc verilator git llvm clang lld protobuf antlr4 numactl`\n- Nix  \n`nix-shell`\n- Ubuntu  \n```shell\napt-get install make parallel wget cmake verilator git llvm clang lld protobuf-compiler antlr4 numactl\ncurl -L https://github.com/com-lihaoyi/mill/releases/download/0.10.8/0.10.8 \u003e mill \u0026\u0026 chmod +x mill\n```\n\u003e We recomment using java 17 or higher versions.\n\n1. Init and update dependences\n\n```shell\nmake init\nmake patch\n```\n\n2. IDE support  `make bsp # generate IDE bsp`\n\n3. to generate verilog file, use `make verilog`. The output file is `GPGPU_top.v` . Notice that if you install 'mill' with 'curl', use `./mill ` to replace `mill` in Makefile commands.\n\n4. to run tests, use `make tests`. Output waveform file is at `test_run_dir`  \n\n\u003e Notice that current codes are not stable and there are conflicts between existing codes and testcase `gaussian` `gemm`. We are preparing new testcase format to integrate with software toolchain and please wait for our new version.\n\n## Acknowledgement\n\nWe refer to some open-source design when developing Ventus GPGPU.\n\n| Sub module                | Source                                                                                                                                              | Detail                                                                         |\n|---------------------------|-----------------------------------------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------|\n| CTA scheduler             | [MIAOW](https://github.com/VerticalResearchGroup/miaow)                                                                                             | Our CTA scheduler module is based on MiaoW ultra-threads dispatcher.           |\n| L2Cache                   | [block-inclusivecache-sifive](https://github.com/sifive/block-inclusivecache-sifive) | Our L2Cache design is inspired by Sifive's block-inclusivecache     |\n| Multiplier                | [XiangShan](https://github.com/OpenXiangShan/XiangShan)                                                                                             | We reused Array Multiplier in XiangShan. FPU design is also inspired by XiangShan. |\n| Config, ... |  [rocket-chip](https://github.com/chipsalliance/rocket-chip)                                                                                                                                         | Some modules are sourced from RocketChip                                       |\n\n\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FTHU-DSP-LAB%2Fventus-gpgpu","html_url":"https://awesome.ecosyste.ms/projects/github.com%2FTHU-DSP-LAB%2Fventus-gpgpu","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FTHU-DSP-LAB%2Fventus-gpgpu/lists"}