{"id":13408114,"url":"https://github.com/TM90/awesome-hwd-tools","last_synced_at":"2025-03-14T12:32:08.695Z","repository":{"id":48288154,"uuid":"158928501","full_name":"TM90/awesome-hwd-tools","owner":"TM90","description":"A curated list of awesome open source hardware design tools","archived":false,"fork":false,"pushed_at":"2024-02-08T10:18:59.000Z","size":57,"stargazers_count":60,"open_issues_count":0,"forks_count":8,"subscribers_count":6,"default_branch":"master","last_synced_at":"2024-04-14T12:16:14.744Z","etag":null,"topics":["asic","awesome-list","design-automation","fpga","hardware"],"latest_commit_sha":null,"homepage":"","language":null,"has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"gpl-3.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/TM90.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null}},"created_at":"2018-11-24T11:13:39.000Z","updated_at":"2024-04-11T09:22:42.000Z","dependencies_parsed_at":"2024-04-04T00:39:02.245Z","dependency_job_id":"4c11c5b9-38fb-44eb-97b4-16e98c32a7e3","html_url":"https://github.com/TM90/awesome-hwd-tools","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/TM90%2Fawesome-hwd-tools","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/TM90%2Fawesome-hwd-tools/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/TM90%2Fawesome-hwd-tools/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/TM90%2Fawesome-hwd-tools/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/TM90","download_url":"https://codeload.github.com/TM90/awesome-hwd-tools/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":243578505,"owners_count":20313840,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["asic","awesome-list","design-automation","fpga","hardware"],"created_at":"2024-07-30T20:00:50.841Z","updated_at":"2025-03-14T12:32:08.678Z","avatar_url":"https://github.com/TM90.png","language":null,"funding_links":[],"categories":["Others","Other Lists","Awesome List","🌍 Awesome Digital IC Resources","Awesome Awesome ⭐"],"sub_categories":["Help","TeX Lists","Physical Design"],"readme":"# awesome-hwd-tools\nA curated list of awesome open source hardware design tools with a focus on chip design.\n\nFor electronic hardware tools without a focus on chip design see:\n\nhttps://github.com/kitspace/awesome-electronics\n\nInspired by [awesome-python](https://github.com/vinta/awesome-python).\n\n## Semi Custom Design/ FPGAs\n\n[Nic30/hdlConverter](https://github.com/Nic30/hdlConvertor) - Python System-Verilog/VHDL Parser\n\n[christiklein/simpy](https://gitlab.com/team-simpy/simpy) - discrite event based simulation framework\n\n[chipmuenk/pyFDA](https://github.com/chipmuenk/pyFDA) - A python tool to design time discrete filters\n\n[efabless/openlane](https://github.com/efabless/openlane) - Automated RTL to GDS flow based on openRoad, Yosys and more...\n\n[ahmed-agiza/EDAViewer](https://github.com/ahmed-agiza/EDAViewer) - EDAV is a cloud-based open-source viewer for electronic design automation (EDA) design files (LEF, DEF)\n\n\n### Modelling\n\n[cornell-brg/pymtl3](https://github.com/cornell-brg/pymtl3) - hardware modeling framework\n\n[mortbopet/VSRTL](https://github.com/mortbopet/VSRTL) - Visual Simulation of Register Transfer Logic\n\n### Hardware Description Languages\n\n[freechipsproject/Chisel](https://github.com/freechipsproject/chisel3/) - Hardware Description Language embedded in Scala developed at UC Berkeley\n\n[phanrahan/Magma](https://github.com/phanrahan/magma) - A Hardware Description Language embedded in Python\n\n[llvm/circt](https://github.com/llvm/circt) - Intermediate representation for rtl (used by Chisel)\n\n[myhdl/MyHDL](https://github.com/myhdl/myhdl) - Python as a Hardware Description and Verification Language\n\n[clash-lang/clash-compiler](https://github.com/clash-lang/clash-compiler) - A Hardware Description Language written and inspired by Haskell\n\nA much more detailed and specific list for hardware description languages can be found at [drom/awesome-hdl](https://github.com/drom/awesome-hdl).\n\n### Wave Viewers\n\n[gtkwave](http://gtkwave.sourceforge.net/) - GTK based waveform viewer\n\n[wavedrom/wavedrom](https://github.com/wavedrom/wavedrom) - Timing Diagrams in Java Script\n\n### Simulation\n\n[steveicarus/iverilog](https://github.com/steveicarus/iverilog) - Icarus Verilog Simulator\n\n[ghdl/ghdl](https://github.com/ghdl/ghdl) - VHDL Simulator\n\n### Synthesis\n\n[YosysHQ/yosys](https://github.com/YosysHQ/yosys) - Synthesis Flow\n\n### Timing Analysis\n\n[abk-openroad/OpenSTA](https://github.com/abk-openroad/OpenSTA) - static timing analysis\n\n[OpenTimer/OpenTimer](https://github.com/OpenTimer/OpenTimer) - timing analysis tool for vlsi systems\n\n### Verification\n\n[YosysHQ/SymbiYosys](https://github.com/YosysHQ/SymbiYosys) - formal verification flow and tool\n\n[cocotb/cocotb](https://github.com/cocotb/cocotb) - Creating Verilog/VHDL testbenches with python \n\n## Open Source PDK\n\n[leviathanch/libresiliconprocess](https://github.com/leviathanch/libresiliconprocess) - A 1um open process specification\n\n[google/skywater-pdk](https://github.com/google/skywater-pdk) - Open Source Process SkyWater 130nm\n\n## Full Custom Design\n\n[heitzmann/gdsstk](https://github.com/heitzmann/gdstk) - Gdstk (GDSII Tool Kit) is a C++/Python library for creation and manipulation of GDSII and OASIS files.\n\n[unihd-cag/skillbridge](https://github.com/unihd-cag/skillbridge) - A seamless python to Cadence Virtuoso Skill interface\n\n[electronics-and-drives/SPAM](https://github.com/electronics-and-drives/SPAM) - SPAM is a package management system for Cadence SKILL\n\n[electronics-and-drives/ml2tikz](https://github.com/electronics-and-drives/ml2tikz) - Virtuoso layout to tikzpicture\n\n[MatthewLoveQUB/SKILL_Tools](https://github.com/MatthewLoveQUB/SKILL_Tools) - Skill++ Tools including a test framework\n\n[EDDRSoftware/oaFileParser](https://github.com/EDDRSoftware/oaFileParser) - oaFile Parser\n\n[scikit-rf/scikit-rf](https://github.com/scikit-rf/scikit-rf) - RF and Microwave Design in scikit\n\n[mph-/lcapy](https://github.com/mph-/lcapy) - Lcapy is a Python package for linear circuit analysis. It uses SymPy for symbolic mathematics.\n\n[YosysHQ/PADRING](https://github.com/YosysHQ/padring) - A padring generator for asics\n\n[DegateCommunity/Degate](https://github.com/DegateCommunity/Degate) - Tool for VLSI reverse engineering\n\n[cap1tan/wafermap](https://github.com/cap1tan/wafermap) - A python package to plot maps of semiconductor wafers\n\n### Layout Generation/ Manipulation\n\n[ucb-art/BAG_framework](https://github.com/ucb-art/BAG_framework) - Berkeley Analog Generator\n\n[VLSIDA/OpenRAM](https://github.com/VLSIDA/OpenRAM) - open-source SRAM Compiler\n\n[KLayout/klayout](https://github.com/KLayout/klayout) - scriptable Layout Viewer and Editor\n\n### Simulation\n\n[ngspice](http://ngspice.sourceforge.net/index.html) - Spice Simulator\n\n[FabriceSalvaire/pyspice](https://github.com/FabriceSalvaire/PySpice) - Simulating and creating Spice Circuits with Python\n\n### Mixed Signal Design \n\n[Isotel/mixedsim](https://github.com/Isotel/mixedsim) - A mixed signal simulation approach using ngspice and yosys providing a library mapping to spice\n\n## Documentation\n\n[SchemDraw](https://bitbucket.org/cdelker/schemdraw/src/master/) - producing circuit diagrams with python\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FTM90%2Fawesome-hwd-tools","html_url":"https://awesome.ecosyste.ms/projects/github.com%2FTM90%2Fawesome-hwd-tools","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FTM90%2Fawesome-hwd-tools/lists"}