{"id":13831500,"url":"https://github.com/The-OpenROAD-Project/yosys","last_synced_at":"2025-07-09T14:33:12.656Z","repository":{"id":43386287,"uuid":"188917318","full_name":"The-OpenROAD-Project/yosys","owner":"The-OpenROAD-Project","description":"Logic synthesis and ABC based optimization","archived":false,"fork":true,"pushed_at":"2024-11-05T13:31:20.000Z","size":28088,"stargazers_count":46,"open_issues_count":0,"forks_count":41,"subscribers_count":10,"default_branch":"master","last_synced_at":"2024-11-05T14:34:14.854Z","etag":null,"topics":["brown-university","logic-synthesis","physical-synthesis"],"latest_commit_sha":null,"homepage":"","language":"C++","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":"YosysHQ/yosys","license":"isc","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/The-OpenROAD-Project.png","metadata":{"files":{"readme":"README.md","changelog":"CHANGELOG","contributing":null,"funding":null,"license":"COPYING","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":"CODEOWNERS","security":null,"support":null,"governance":null}},"created_at":"2019-05-27T22:41:57.000Z","updated_at":"2024-11-05T13:31:39.000Z","dependencies_parsed_at":"2023-02-09T13:01:27.406Z","dependency_job_id":null,"html_url":"https://github.com/The-OpenROAD-Project/yosys","commit_stats":null,"previous_names":[],"tags_count":33,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/The-OpenROAD-Project%2Fyosys","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/The-OpenROAD-Project%2Fyosys/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/The-OpenROAD-Project%2Fyosys/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/The-OpenROAD-Project%2Fyosys/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/The-OpenROAD-Project","download_url":"https://codeload.github.com/The-OpenROAD-Project/yosys/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":225565813,"owners_count":17489270,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["brown-university","logic-synthesis","physical-synthesis"],"created_at":"2024-08-04T10:01:29.476Z","updated_at":"2025-07-09T14:33:12.650Z","avatar_url":"https://github.com/The-OpenROAD-Project.png","language":"C++","funding_links":[],"categories":["C++"],"sub_categories":[],"readme":"yosys – Yosys Open SYnthesis Suite\n===================================\n\nThis is a framework for RTL synthesis tools. It currently has\nextensive Verilog-2005 support and provides a basic set of\nsynthesis algorithms for various application domains.\n\nYosys can be adapted to perform any synthesis job by combining\nthe existing passes (algorithms) using synthesis scripts and\nadding additional passes as needed by extending the yosys C++\ncode base.\n\nYosys is free software licensed under the ISC license (a GPL\ncompatible license that is similar in terms to the MIT license\nor the 2-clause BSD license).\n\nThird-party software distributed alongside this software\nis licensed under compatible licenses.\nPlease refer to `abc` and `libs` subdirectories for their license terms.\n\n\nWeb Site and Other Resources\n============================\n\nMore information and documentation can be found on the Yosys web site:\n- https://yosyshq.net/yosys/\n\nDocumentation from this repository is automatically built and available on Read\nthe Docs:\n- https://yosyshq.readthedocs.io/projects/yosys\n\nUsers interested in formal verification might want to use the formal\nverification front-end for Yosys, SBY:\n- https://yosyshq.readthedocs.io/projects/sby/\n- https://github.com/YosysHQ/sby\n\n\nInstallation\n============\n\nYosys is part of the [Tabby CAD Suite](https://www.yosyshq.com/tabby-cad-datasheet) and the [OSS CAD Suite](https://github.com/YosysHQ/oss-cad-suite-build)! The easiest way to use yosys is to install the binary software suite, which contains all required dependencies and related tools.\n\n* [Contact YosysHQ](https://www.yosyshq.com/contact) for a [Tabby CAD Suite](https://www.yosyshq.com/tabby-cad-datasheet) Evaluation License and download link\n* OR go to https://github.com/YosysHQ/oss-cad-suite-build/releases to download the free OSS CAD Suite\n* Follow the [Install Instructions on GitHub](https://github.com/YosysHQ/oss-cad-suite-build#installation)\n\nMake sure to get a Tabby CAD Suite Evaluation License if you need features such as industry-grade SystemVerilog and VHDL parsers!\n\nFor more information about the difference between Tabby CAD Suite and the OSS CAD Suite, please visit https://www.yosyshq.com/tabby-cad-datasheet\n\nMany Linux distributions also provide Yosys binaries, some more up to date than others. Check with your package manager!\n\n\nBuilding from Source\n====================\n\nFor more details, and instructions for other platforms, check [building from\nsource](https://yosyshq.readthedocs.io/projects/yosys/en/latest/getting_started/installation.html#building-from-source)\non Read the Docs.\n\nWhen cloning Yosys, some required libraries are included as git submodules. Make\nsure to call e.g.\n\n\t$ git clone --recurse-submodules https://github.com/YosysHQ/yosys.git\n\nor\n\n\t$ git clone https://github.com/YosysHQ/yosys.git\n\t$ cd yosys\n\t$ git submodule update --init --recursive\n\nYou need a C++ compiler with C++17 support (up-to-date CLANG or GCC is\nrecommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make.\nTCL, readline and libffi are optional (see ``ENABLE_*`` settings in Makefile).\nXdot (graphviz) is used by the ``show`` command in yosys to display schematics.\n\nFor example on Ubuntu Linux 16.04 LTS the following commands will install all\nprerequisites for building yosys:\n\n\t$ sudo apt-get install build-essential clang lld bison flex \\\n\t\tlibreadline-dev gawk tcl-dev libffi-dev git \\\n\t\tgraphviz xdot pkg-config python3 libboost-system-dev \\\n\t\tlibboost-python-dev libboost-filesystem-dev zlib1g-dev\n\nThe environment variable `CXX` can be used to control the C++ compiler used, or\nrun one of the following to override it:\n\n\t$ make config-clang\n\t$ make config-gcc\n\nThe Makefile has many variables influencing the build process. These can be\nadjusted by modifying the Makefile.conf file which is created at the `make\nconfig-...` step (see above), or they can be set by passing an option to the\nmake command directly:\n\n  $ make CXX=$CXX\n\nFor other compilers and build configurations it might be necessary to make some\nchanges to the config section of the Makefile. It's also an alternative way to\nset the make variables mentioned above.\n\n\t$ vi Makefile            # ..or..\n\t$ vi Makefile.conf\n\nTo build Yosys simply type 'make' in this directory.\n\n\t$ make\n\t$ sudo make install\n\nTests are located in the tests subdirectory and can be executed using the test\ntarget. Note that you need gawk as well as a recent version of iverilog (i.e.\nbuild from git). Then, execute tests via:\n\n\t$ make test\n\nTo use a separate (out-of-tree) build directory, provide a path to the Makefile.\n\n\t$ mkdir build; cd build\n\t$ make -f ../Makefile\n\nOut-of-tree builds require a clean source tree.\n\n\nGetting Started\n===============\n\nYosys can be used with the interactive command shell, with\nsynthesis scripts or with command line arguments. Let's perform\na simple synthesis job using the interactive command shell:\n\n\t$ ./yosys\n\tyosys\u003e\n\nthe command ``help`` can be used to print a list of all available\ncommands and ``help \u003ccommand\u003e`` to print details on the specified command:\n\n\tyosys\u003e help help\n\nreading and elaborating the design using the Verilog frontend:\n\n\tyosys\u003e read -sv tests/simple/fiedler-cooley.v\n\tyosys\u003e hierarchy -top up3down5\n\nwriting the design to the console in the RTLIL format used by Yosys\ninternally:\n\n\tyosys\u003e write_rtlil\n\nconvert processes (``always`` blocks) to netlist elements and perform\nsome simple optimizations:\n\n\tyosys\u003e proc; opt\n\ndisplay design netlist using ``xdot``:\n\n\tyosys\u003e show\n\nthe same thing using ``gv`` as postscript viewer:\n\n\tyosys\u003e show -format ps -viewer gv\n\ntranslating netlist to gate logic and perform some simple optimizations:\n\n\tyosys\u003e techmap; opt\n\nwrite design netlist to a new Verilog file:\n\n\tyosys\u003e write_verilog synth.v\n\nor using a simple synthesis script:\n\n\t$ cat synth.ys\n\tread -sv tests/simple/fiedler-cooley.v\n\thierarchy -top up3down5\n\tproc; opt; techmap; opt\n\twrite_verilog synth.v\n\n\t$ ./yosys synth.ys\n\nIf ABC is enabled in the Yosys build configuration and a cell library is given\nin the liberty file ``mycells.lib``, the following synthesis script will\nsynthesize for the given cell library:\n\n\t# read design\n\tread -sv tests/simple/fiedler-cooley.v\n\thierarchy -top up3down5\n\n\t# the high-level stuff\n\tproc; fsm; opt; memory; opt\n\n\t# mapping to internal cell library\n\ttechmap; opt\n\n\t# mapping flip-flops to mycells.lib\n\tdfflibmap -liberty mycells.lib\n\n\t# mapping logic to mycells.lib\n\tabc -liberty mycells.lib\n\n\t# cleanup\n\tclean\n\nIf you do not have a liberty file but want to test this synthesis script,\nyou can use the file ``examples/cmos/cmos_cells.lib`` from the yosys sources\nas simple example.\n\nLiberty file downloads for and information about free and open ASIC standard\ncell libraries can be found here:\n\n- http://www.vlsitechnology.org/html/libraries.html\n- http://www.vlsitechnology.org/synopsys/vsclib013.lib\n\nThe command ``synth`` provides a good default synthesis script (see\n``help synth``):\n\n\tread -sv tests/simple/fiedler-cooley.v\n\tsynth -top up3down5\n\n\t# mapping to target cells\n\tdfflibmap -liberty mycells.lib\n\tabc -liberty mycells.lib\n\tclean\n\nThe command ``prep`` provides a good default word-level synthesis script, as\nused in SMT-based formal verification.\n\n\nAdditional information\n======================\n\nThe ``read_verilog`` command, used by default when calling ``read`` with Verilog\nsource input, does not perform syntax checking.  You should instead lint your\nsource with another tool such as\n[Verilator](https://www.veripool.org/verilator/) first, e.g. by calling\n``verilator --lint-only``.\n\n\nBuilding the documentation\n==========================\n\nNote that there is no need to build the manual if you just want to read it.\nSimply visit https://yosys.readthedocs.io/en/latest/ instead.\n\nIn addition to those packages listed above for building Yosys from source, the\nfollowing are used for building the website: \n\n\t$ sudo apt install pdf2svg faketime\n\nOr for MacOS, using homebrew:\n\n  $ brew install pdf2svg libfaketime\n\nPDFLaTeX, included with most LaTeX distributions, is also needed during the\nbuild process for the website.  Or, run the following:\n\n\t$ sudo apt install texlive-latex-base texlive-latex-extra latexmk\n\nOr for MacOS, using homebrew:\n\n  $ brew install basictex\n  $ sudo tlmgr update --self   \n  $ sudo tlmgr install collection-latexextra latexmk tex-gyre\n\nThe Python package, Sphinx, is needed along with those listed in\n`docs/source/requirements.txt`:\n\n\t$ pip install -U sphinx -r docs/source/requirements.txt\n\nFrom the root of the repository, run `make docs`.  This will build/rebuild yosys\nas necessary before generating the website documentation from the yosys help\ncommands.  To build for pdf instead of html, call \n`make docs DOC_TARGET=latexpdf`.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FThe-OpenROAD-Project%2Fyosys","html_url":"https://awesome.ecosyste.ms/projects/github.com%2FThe-OpenROAD-Project%2Fyosys","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FThe-OpenROAD-Project%2Fyosys/lists"}