{"id":13417289,"url":"https://github.com/UVVM/UVVM","last_synced_at":"2025-03-15T02:30:53.749Z","repository":{"id":3546310,"uuid":"50093478","full_name":"UVVM/UVVM","owner":"UVVM","description":"UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement.    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The VVC Framework and VVCs for medium to advanced testbenches, and the Utility library and BFMs for simple usage - and as a basis for more advanced testbenches.\nNovice users are strongly recommended to first use UVVM Utility library and BFMs. This has a *very* low user threshold and you will be up and running in an hour. Please see [Utility Library](./uvvm_util/README.md) for an introduction. \nThe VVC framework is slightly more complex, but it has been simplified as far as possible to allow efficient development of good quality testbenches.\nAs a starter you may also want to include Enhanced Randomisation, Functional Coverage or Specification coverage\n\nNote that a dedicated repository (UVVM_Light)](https://github.com/UVVM/UVVM_Light) has been provided to simplify getting started using Utility Library and BFMs. Here all the code and documentation have been collected in a single directory, and only a single VHDL library is used. The documentation and code are 100% the same as for the full UVVM. \n\nPlease also see [Getting Started](./GETTING_STARTED.md) with UVVM.\n\n## For what do I need this VVC Framework?\nUVVM is a verification component system that allows the implementation of a very structured testbench architecture to handle any verification complexity - from really simple to really complex. A key benefit of this system is the very simple software-like VHDL test sequencer that may control your complete testbench architecture with any number of verification components. This takes overview, readability and maintainability to a new level.\nAs an example a simple command like uart_expect(UART_VVCT, my_data), or axilite_write(AXILITE_VVCT, my_addr, my_data, my_message) will automatically tell the respective VVC (for UART or AXI-Lite) to execute the uart_receive() or axilite_write() BFM respectively.\n\n## What are the main benefits of using this system?\nThe really great benefit here is the unique overview, readability, maintainability, extensibility and reuse you get from having the best testbench architecture possible - much in the same way as a good architecture is also critical for any complex FPGA design.\nAnother major benefit here is that any number of commands may be issued at the same time from the test sequencer - thus allowing full control of when an access is to be performed, and the commands are understandable \"even\" for a software developer ;-)   The commands may be queued, skewed, delayed, synchronised, etc. - and a super-set for applying constrained random or other sequences of data may of course also be applied.\nThis yields an excellent control over your testbench and VVCs.\n\nFor debugging you can select logging of a command when it is issued from the sequencer, when it is received by the VVC, when it is initiated by the VVC and/or when it has been executed towards the DUT. This allows full overview of all actions in your complete testbench.\n\nUVVM is free and open source and has standardised the way to build good testbench architectures and VVCs so that reuse is dead simple, and allows the FPGA community to share VVCs that will work together in a well-structured test harness.\nYou may of course combine UVVM with any other legacy or 3rd party testbenches or verification models.\n\n\n## Main Features\n*\tVery useful support for checking values, ranges, time aspects, and for waiting for events inside a given window\n*\tAn extremely low user threshold for the basic functionality - like logging, alert handling and checkers\n*\tA very structured testbench architecture that allows LEGO-like testbench/harness implementation\n*\tA very structured VHDL Verification Component (VVC) architecture that allows simultaneous activity (stimuli and checking) on multiple interfaces in a very easily understandable manner\n*\tAn easily understandable command syntax to control a complete testbench with multiple VVCs\n*\tThe structure and overview are easily kept even for a testbench with a large number of VVCs\n*\tA VVC architecture that is almost exactly the same from one VVC to another - sometimes with only the BFM calls as the differentiator, thus allowing an extremely efficient reuse from one VVC to another\n*\tA VVC architecture that easily allows multiple threads for e.g. simultaneous Avalon Command and Response\n*\tA VVC architecture that allows simple encapsulation for ALL verification functionality for any given interface or protocol\n*\tAllows VVCs to be included anywhere in the test harness - or even inside the design itself\n*\tA logging and alert system that supports full verbosity control of functionality and hierarchy\n*\tA logging system that lets you easily see how your commands propagate from your central test sequencer to your VVCs - through the execution queue - until it is executed and completed towards the DUT\n*\tIncludes randomisation and functional coverage to be included in the central test sequencer - or even better - inside the VVCs in the local sequencers for better control and encapsulation\n*\tSimple integration with regression test tools like Jenkins and [HDLRegression](https://github.com/HDLUtils/hdlregression)\n*\tQuick references are available for UVVM Utility Library, VVC Framework and all the BFMs/VVCs/VIP\n*   May insert delay between commands – from sequencer, - and thus the only system to target cycle related corner cases\n*   Simple handling of split transactions and out of order protocols\n*   Common commands to control VVC behaviour\n*   Simple synchronization of interface actions – from sequencer\n*   May use Broadcast and Multicast\n\n\n\n## Available VVCs and BFMs\nThese VVCs and BFMs could be used inside a typical UVVM testbench, but they could also be used stand-alone - e.g. as a BFM or VVC to handle just the AXI4-Lite interface with everything else being your proprietary testbench and methodology.\n*\tAXI4\n*\tAXI4-Lite\n*\tAXI-Stream - master and slave\n*\tAvalon MM\n*   Avalon ST - master and slave\n*   Ethernet\n*\tSBI (Simple Bus Interface - A single cycle simple parallel bus interface)\n*\tUART\n*\tSPI - master and slave\n*\tI2C - master and slave\n*   GPIO\n*   GMII - Transmit and receive\n*   RGMII - Transmit and receive\n*   Wishbone\n*   Clock Generator\n*   Error Injector\n*\tMore are coming\n\n**IMPORTANT**\nThe VIPs complies with respective protocols and thus allows a\nnormal access towards the interface. The VIPs are not protocol checkers.\n\n## Prerequisites\nUVVM is tool and library independent, but it must be compiled with VHDL-2008 or newer.\nUVVM has been tested with the following simulators:\n- Modelsim\n- Riviera-PRO\n- Questa Sim\n- GHDL\n\n**Note** Questa Sim version 19.2 and Modelsim version 19.2 have known bugs that might prevent UVVM from working properly.\n\nPython is required **if** you want to execute the VVC generation scripts\n\n\n## Introduction to VVC Framework - including manuals\nAll documents including powerpoint presentations are available in the *doc* (and *uvvm_vvc_framework/doc*) directory on GitHub.\nThese are just fast access links to some interesting info:\n- *['The critically missing VHDL testbench feature - Finally a structured approach'* - A brief introduction](./uvvm_vvc_framework/doc/The_critically_missing_VHDL_TB_feature.ppsx)\n- *['VVC Framework Manual'*  - The user manual](./uvvm_vvc_framework/doc/VVC_Framework_Manual.pdf)\n\n\n## License\n\nCopyright 2024 UVVM  \nLicensed under the Apache License, Version 2.0 (the \"License\"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.\n\nUnless required by applicable law or agreed to in writing, software distributed under the License is distributed on an \"AS IS\" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.\n\n\n## UVVM Maintainers\nThe UVVM steering group (currently Inventas and EmLogic, Norway) has released UVVM as open source and both EmLogic and Inventas are committed to develop this system further.\nWe do however appreciate contributions and suggestions from users.\n\nPlease use Pull requests for contributions and we will evaluate them for inclusion in our release on the master branch.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FUVVM%2FUVVM","html_url":"https://awesome.ecosyste.ms/projects/github.com%2FUVVM%2FUVVM","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FUVVM%2FUVVM/lists"}