{"id":13649285,"url":"https://github.com/VLSI-EDA/PoC","last_synced_at":"2025-04-22T14:31:14.152Z","repository":{"id":24679407,"uuid":"28090247","full_name":"VLSI-EDA/PoC","owner":"VLSI-EDA","description":"IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany","archived":false,"fork":false,"pushed_at":"2020-11-29T14:01:37.000Z","size":5196,"stargazers_count":577,"open_issues_count":36,"forks_count":103,"subscribers_count":58,"default_branch":"master","last_synced_at":"2025-04-18T21:25:40.660Z","etag":null,"topics":["altera","asic","fpga","hardware-designs","hardware-libraries","hardware-modules","lattice","osvvm","poc-library","python","regression-testing","simulation","synthesis","testbenches","uvvm","verification","vhdl","vlsi","vunit","xilinx"],"latest_commit_sha":null,"homepage":"https://tu-dresden.de/ing/informatik/ti/vlsi","language":"VHDL","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/VLSI-EDA.png","metadata":{"files":{"readme":"README.md","changelog":"CHANGES.md","contributing":".github/CONTRIBUTING.md","funding":null,"license":"LICENSE.md","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2014-12-16T14:21:05.000Z","updated_at":"2025-04-03T14:40:17.000Z","dependencies_parsed_at":"2022-08-23T07:50:43.574Z","dependency_job_id":null,"html_url":"https://github.com/VLSI-EDA/PoC","commit_stats":null,"previous_names":[],"tags_count":10,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/VLSI-EDA%2FPoC","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/VLSI-EDA%2FPoC/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/VLSI-EDA%2FPoC/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/VLSI-EDA%2FPoC/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/VLSI-EDA","download_url":"https://codeload.github.com/VLSI-EDA/PoC/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":250258908,"owners_count":21400994,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["altera","asic","fpga","hardware-designs","hardware-libraries","hardware-modules","lattice","osvvm","poc-library","python","regression-testing","simulation","synthesis","testbenches","uvvm","verification","vhdl","vlsi","vunit","xilinx"],"created_at":"2024-08-02T01:04:55.634Z","updated_at":"2025-04-22T14:31:09.136Z","avatar_url":"https://github.com/VLSI-EDA.png","language":"VHDL","funding_links":[],"categories":["IP Core Libraries","VHDL"],"sub_categories":[],"readme":"\u003c!--- DO NOT EDIT! This file is generated from .tpl ---\u003e\n# The PoC-Library\n\n[![Build Status by Travis-CI](https://travis-ci.org/VLSI-EDA/PoC.svg?branch=release)](https://travis-ci.org/VLSI-EDA/PoC/branches)\n[![Build status by AppVeyor](https://ci.appveyor.com/api/projects/status/r5dtv6amsppigpsp/branch/release?svg=true)](https://ci.appveyor.com/project/Paebbels/poc/branch/release)\n[![Documentation Status](https://readthedocs.org/projects/poc-library/badge/?version=latest)](http://poc-library.readthedocs.io/en/latest/?badge=latest)\n[![Python Infrastructure tested by Landscape.io](https://landscape.io/github/VLSI-EDA/PoC/release/landscape.svg?style=flat)](https://landscape.io/github/VLSI-EDA/PoC/release)\n[![Requirements Status](https://requires.io/github/VLSI-EDA/PoC/requirements.svg?branch=release)](https://requires.io/github/VLSI-EDA/PoC/requirements/?branch=release) [![FOSSA Status](https://app.fossa.io/api/projects/git%2Bgithub.com%2FVLSI-EDA%2FPoC.svg?type=shield)](https://app.fossa.io/projects/git%2Bgithub.com%2FVLSI-EDA%2FPoC?ref=badge_shield)\n \n[![Join the chat at https://gitter.im/VLSI-EDA/PoC](https://badges.gitter.im/VLSI-EDA/PoC.svg)](https://gitter.im/VLSI-EDA/PoC)\n[![Subscribe for news at https://gitter.im/VLSI-EDA/News](https://img.shields.io/badge/news-Subscribe%20to%20VLSI--EDA%2FNews-orange.svg)](https://gitter.im/VLSI-EDA/News)  \n![Latest tag](https://img.shields.io/github/tag/VLSI-EDA/PoC.svg?style=flat)\n[![Latest release](https://img.shields.io/github/release/VLSI-EDA/PoC.svg?style=flat)](https://github.com/VLSI-EDA/PoC/releases)\n[![Apache License 2.0](https://img.shields.io/github/license/VLSI-EDA/PoC.svg?style=flat)](LICENSE.md)\n\n\nThis library is published and maintained by **Chair for VLSI Design, Diagnostics and Architecture** - \nFaculty of Computer Science, Technische Universität Dresden, Germany \n**http://vlsi-eda.inf.tu-dresden.de**\n\n![Technische Universität Dresden](https://github.com/VLSI-EDA/PoC/wiki/images/logo_tud.gif)\n\nTable of Content:\n--------------------------------------------------------------------------------\n 1. [Overview](#1-overview)\n 2. [Quick Start Guide](#2-quick-start-guide)  \n    2.1. [Requirements and Dependencies](#21-requirements-and-dependencies)  \n    2.2. [Download](#22-download)  \n    2.3. [Configuring PoC on a Local System](#23-configuring-poc-on-a-local-system)  \n    2.4. [Integration](#24-integration)  \n    2.5. [Updating](#25-updating)\n 3. [Common Notes](#3-common-notes)\n 4. [Cite the PoC-Library](#4-cite-the-poc-library)\n\n--------------------------------------------------------------------------------\n\n## 1 Overview\n\nPoC - “Pile of Cores” provides implementations for often required hardware functions such as\nArithmetic Units, Caches, Clock-Domain-Crossing Circuits, FIFOs, RAM wrappers, and I/O Controllers.\nThe hardware modules are typically provided as VHDL or Verilog source code, so it can be easily\nre-used in a variety of hardware designs.\n\nAll hardware modules use a common set of VHDL packages to share new VHDL types, sub-programs and\nconstants. Additionally, a set of simulation helper packages eases the writing of testbenches.\nBecause PoC hosts a huge amount of IP cores, all cores are grouped into sub-namespaces to build a\nclear hierachy.\n\nVarious simulation and synthesis tool chains are supported to interoperate with PoC. To generalize\nall supported free and commercial vendor tool chains, PoC is shipped with a Python based\ninfrastructure to offer a command line based frontend.\n\n\n## 2 Quick Start Guide\n\nThis **Quick Start Guide** gives a fast and simple introduction into PoC. All topics can be found in\nthe [Using PoC][201] section at [ReadTheDocs.io][202] with much more details and examples.\n\n\n### 2.1 Requirements and Dependencies\n\nThe PoC-Library comes with some scripts to ease most of the common tasks, like running testbenches or\ngenerating IP cores. PoC uses Python 3 as a platform independent scripting environment. All Python\nscripts are wrapped in Bash or PowerShell scripts, to hide some platform specifics of Darwin, Linux or\nWindows. See [Requirements][211] for further details.\n\n[211]: http://poc-library.readthedocs.io/en/latest/UsingPoC/Requirements.html\n\n\n#### PoC requires:\n -  A [supported synthesis tool chain][2111], if you want to synthezise IP cores.\n -  A [supported simulator tool chain][2112], if you want to simulate IP cores.\n -  The **Python 3** programming language and runtime, if you want to use PoC's infrastructure.\n -  A shell to execute shell scripts:\n    -  **Bash** on Linux and OS X\n    -  **PowerShell** on Windows\n\n[2111]: http://poc-library.readthedocs.io/en/latest/WhatIsPoC/SupportedToolChains.html\n[2112]: http://poc-library.readthedocs.io/en/latest/WhatIsPoC/SupportedToolChains.html\n\n\n#### PoC optionally requires:\n -  **Git command line** tools or\n -  **Git User Interface**, if you want to check out the latest 'master' or 'release' branch.\n\n\n#### PoC depends on third part libraries:\n -  [Cocotb][2131]  \n    A coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python.\n -  [OS-VVM][2132]  \n    Open Source VHDL Verification Methodology.\n -  [UVVM][2133]  \n    Universal VHDL Verification Methodology.\n -  [VUnit][2134]  \n    An unit testing framework for VHDL.\n  \nAll dependencies are available as GitHub repositories and are linked to PoC as Git submodules into the\n[`PoCRoot\\lib`][205] directory. See [Third Party Libraries][206] for more details on these libraries.\n\n[2131]: https://github.com/potentialventures/cocotb\n[2132]: https://github.com/JimLewis/OSVVM\n[2133]: https://github.com/UVVM/UVVM_All\n[2134]: https://github.com/VUnit/vunit\n\n[201]: http://poc-library.readthedocs.io/en/latest/UsingPoC/index.html\n[202]: http://poc-library.readthedocs.io/\n[205]: https://github.com/VLSI-EDA/PoC/tree/release/lib\n[206]: http://poc-library.readthedocs.io/en/latest/Miscelaneous/ThirdParty.html\n\n\n### 2.2 Download\n\nThe PoC-Library can be downloaded as a [zip-file][221] (latest 'release' branch), cloned with `git clone`\nor embedded with `git submodule add` from GitHub. GitHub offers HTTPS and SSH as transfer protocols. See\nthe [Download][222] page for further details. The installation directory is referred to as `PoCRoot`.\n\nProtocol | Git Clone Command\n-------- | :-----------------------------------------------------------\nHTTPS    | `git clone --recursive https://github.com/VLSI-EDA/PoC.git PoC`\nSSH      | `git clone --recursive ssh://git@github.com:VLSI-EDA/PoC.git PoC`\n\n[221]: https://github.com/VLSI-EDA/PoC/archive/release.zip\n[222]: http://poc-library.readthedocs.io/en/latest/UsingPoC/Download.html\n\n### 2.3 Configuring PoC on a Local System\n\nTo explore PoC's full potential, it's required to configure some paths and synthesis or simulation tool\nchains. The following commands start a guided configuration process. Please follow the instructions on\nscreen. It's possible to relaunch the process at any time, for example to register new tools or to update\ntool versions. See [Configuration][231] for more details. Run the following command line instructions to\nconfigure PoC on your local system:\n\n```PowerShell\ncd PoCRoot\n.\\poc.ps1 configure\n```\n\nUse the keyboard buttons: `Y` to accept, `N` to decline, `P` to skip/pass a step and `Return` to accept\na default value displayed in brackets.\n\n[231]: http://poc-library.readthedocs.io/en/latest/UsingPoC/PoCConfiguration.html\n\n### 2.4 Integration\n\nThe PoC-Library is meant to be integrated into other HDL projects. Therefore it's recommended to create\na library folder and add the PoC-Library as a Git submodule. After the repository linking is done, some\nshort configuration steps are required to setup paths, tool chains and the target platform. The following\ncommand line instructions show a short example on how to integrate PoC.\n\n#### a) Adding the Library as a Git submodule\n\nThe following command line instructions will create the folder `lib\\PoC\\` and clone the PoC-Library as a\n[Git submodule][2411] into that folder. `ProjectRoot` is the directory of the hosting Git. A detailed list\nof steps can be found at [Integration][2412].\n\n```powershell\ncd ProjectRoot\nmkdir lib | cd\ngit submodule add https://github.com:VLSI-EDA/PoC.git PoC\ncd PoC\ngit remote rename origin github\ncd ..\\..\ngit add .gitmodules lib\\PoC\ngit commit -m \"Added new git submodule PoC in 'lib\\PoC' (PoC-Library).\"\n```\n\n[2411]: http://git-scm.com/book/en/v2/Git-Tools-Submodules\n[2412]: http://poc-library.readthedocs.io/en/latest/UsingPoC/Integration.html\n\n#### b) Configuring PoC\n\nThe PoC-Library should be configured to explore its full potential. See [Configuration][2421] for more\ndetails. The following command lines will start the configuration process:\n\n```powershell\ncd ProjectRoot\n.\\lib\\PoC\\poc.ps1 configure\n```\n\n[2421]: http://poc-library.readthedocs.io/en/latest/UsingPoC/PoCConfiguration.html\n\n#### c) Creating PoC's `my_config.vhdl` and `my_project.vhdl` Files\n\nThe PoC-Library needs two VHDL files for its configuration. These files are used to determine the most\nsuitable implementation depending on the provided target information. Copy the following two template\nfiles into your project's source folder. Rename these files to \\*.vhdl and configure the VHDL constants\nin the files:\n\n```powershell\ncd ProjectRoot\ncp lib\\PoC\\src\\common\\my_config.vhdl.template src\\common\\my_config.vhdl\ncp lib\\PoC\\src\\common\\my_project.vhdl.template src\\common\\my_project.vhdl\n```\n\n[my_config.vhdl](https://github.com/VLSI-EDA/PoC/blob/release/src/common/my_config.vhdl.template) defines\ntwo global constants, which need to be adjusted:\n\n```vhdl\nconstant MY_BOARD            : string := \"CHANGE THIS\"; -- e.g. Custom, ML505, KC705, Atlys\nconstant MY_DEVICE           : string := \"CHANGE THIS\"; -- e.g. None, XC5VLX50T-1FF1136, EP2SGX90FF1508C3\n```\n\n[my_project.vhdl](https://github.com/VLSI-EDA/PoC/blob/release/src/common/my_project.vhdl.template) also\ndefines two global constants, which need to be adjusted:\n\n```vhdl\nconstant MY_PROJECT_DIR      : string := \"CHANGE THIS\"; -- e.g. d:/vhdl/myproject/, /home/me/projects/myproject/\"\nconstant MY_OPERATING_SYSTEM : string := \"CHANGE THIS\"; -- e.g. WINDOWS, LINUX\n```\n\nFurther informations are provided at [Creating my_config/my_project.vhdl][2431].\n\n[2431]: http://poc-library.readthedocs.io/en/latest/UsingPoC/VHDLConfiguration.html\n\n#### d) Adding PoC's Common Packages to a Synthesis or Simulation Project\n\nPoC is shipped with a set of common packages, which are used by most of its modules. These packages are\nstored in the `PoCRoot\\src\\common` directory. PoC also provides a VHDL context in `common.vhdl` , which\ncan be used to reference all packages at once.\n\n\n#### e) Adding PoC's Simulation Packages to a Simulation Project\n\nSimulation projects additionally require PoC's simulation helper packages, which are located in the\n`PoCRoot\\src\\sim` directory. Because some VHDL version are incompatible among each other, PoC uses\nversion suffixes like `*.v93.vhdl` or `*.v08.vhdl` in the file name to denote the supported VHDL version\nof a file.\n\n\n#### f) Compiling Shipped IP Cores\n\nSome IP Cores are shipped as pre-configured vendor IP Cores. If such IP cores shall be used in a HDL\nproject, it's recommended to use PoC to create, compile and if needed patch these IP cores. See\n[Synthesis][2461] for more details.\n\n[2461]: http://poc-library.readthedocs.io/en/latest/UsingPoC/Synthesis.html\n\n\n### 2.5 Updating\n\nThe PoC-Library can be updated by using `git fetch` and `git merge`.\n\n```PowerShell\ncd PoCRoot\n# update the local repository\ngit fetch --prune\n# review the commit tree and messages, using the 'treea' alias\ngit treea\n# if all changes are OK, do a fast-forward merge\ngit merge\n```\n\n**See also:**\n -  [**Running one or more testbenches**][251]  \n    The installation can be checked by running one or more of PoC's testbenches.\n -  [**Running one or more netlist generation flows**][252]  \n    The installation can also be checked by running one or more of PoC's synthesis flows.\n\n[251]: http://poc-library.readthedocs.io/en/latest/UsingPoC/Simulation.html\n[252]: http://poc-library.readthedocs.io/en/latest/UsingPoC/Synthesis.html \n\n\n## 3. Common Notes\n\n**The PoC-Library** is structured into several sub-folders naming the purpose of the folder like\n[`src`](src) for sources files or [`tb`](tb) for testbench files. The structure within these folders\nis always the same and based on PoC's sub-namespace tree.\n\n**Main directory overview:**\n\n -  [`lib`](lib) - Embedded or linked external libraries.\n -  [`netlist`](netlist) - Configuration files and output directory for pre-configured netlist synthesis\n    results from vendor IP cores or from complex PoC controllers.\n -  [`py`](py) - Supporting Python scripts.\n -  [`sim`](sim) - Pre-configured waveform views for selected testbenches.\n -  [`src`](src) - PoC's source files grouped into sub-folders according to the sub-namespace tree.\n -  [`tb`](tb) - Testbench files.\n -  [`tcl`](tcl) - Tcl files.\n -  [`temp`](temp) - Automatically created temporary directors for various tools used by PoC's Python scripts.\n -  [`tools`](tools) - Settings/highlighting files and helpers for supported tools.\n -  [`ucf`](ucf) - Pre-configured constraint files (\\*.ucf, \\*.xdc, \\*.sdc) for supported FPGA boards.\n -  [`xst`](xst) - Configuration files to synthesize PoC modules with Xilinx XST into a netlist.\n\n\nAll VHDL source files should be compiled into the VHDL library `PoC`. If not indicated otherwise, all\nsource files can be compiled using the VHDL-93 or VHDL-2008 language version. Incompatible files are\nnamed `*.v93.vhdl` and `*.v08.vhdl` to denote the highest supported language version.\n\n\n## 4 Cite the PoC-Library\n\nIf you are using the PoC-Library, please let us know. We are grateful for your project's reference.\nThe PoC-Library hosted at [GitHub.com](https://www.github.com). Please use the following\n[biblatex](https://www.ctan.org/pkg/biblatex) entry to cite us:\n\n```bibtex\n# BibLaTex example entry\n@online{poc,\n  title={{PoC - Pile of Cores}},\n  author={{Chair of VLSI Design, Diagnostics and Architecture}},\n  organization={{Technische Universität Dresden}},\n  year={2016},\n  url={https://github.com/VLSI-EDA/PoC},\n  urldate={2016-10-28},\n}\n```\n\n\n## License\n[![FOSSA Status](https://app.fossa.io/api/projects/git%2Bgithub.com%2FVLSI-EDA%2FPoC.svg?type=large)](https://app.fossa.io/projects/git%2Bgithub.com%2FVLSI-EDA%2FPoC?ref=badge_large)","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FVLSI-EDA%2FPoC","html_url":"https://awesome.ecosyste.ms/projects/github.com%2FVLSI-EDA%2FPoC","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FVLSI-EDA%2FPoC/lists"}