{"id":13996095,"url":"https://github.com/ZipCPU/dpll","last_synced_at":"2025-07-22T23:31:07.491Z","repository":{"id":49847727,"uuid":"113078990","full_name":"ZipCPU/dpll","owner":"ZipCPU","description":"A collection of phase locked loop (PLL) related projects","archived":false,"fork":false,"pushed_at":"2024-01-18T16:22:26.000Z","size":707,"stargazers_count":99,"open_issues_count":0,"forks_count":26,"subscribers_count":10,"default_branch":"master","last_synced_at":"2024-11-29T19:38:22.429Z","etag":null,"topics":["fpga","gplv3","pll","verilator","verilog"],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/ZipCPU.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null}},"created_at":"2017-12-04T18:25:21.000Z","updated_at":"2024-10-27T12:21:54.000Z","dependencies_parsed_at":"2022-08-21T23:01:19.560Z","dependency_job_id":"a011dbd2-3f8b-4836-9e75-35c18700b4a3","html_url":"https://github.com/ZipCPU/dpll","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/ZipCPU/dpll","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Fdpll","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Fdpll/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Fdpll/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Fdpll/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/ZipCPU","download_url":"https://codeload.github.com/ZipCPU/dpll/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Fdpll/sbom","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":266590034,"owners_count":23952854,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","status":"online","status_checked_at":"2025-07-22T02:00:09.085Z","response_time":66,"last_error":null,"robots_txt_status":null,"robots_txt_updated_at":null,"robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["fpga","gplv3","pll","verilator","verilog"],"created_at":"2024-08-09T14:03:48.728Z","updated_at":"2025-07-22T23:31:06.908Z","avatar_url":"https://github.com/ZipCPU.png","language":"Verilog","readme":"I'd like to [post](http://zipcpu.com) about some simple and some basic\n[Phase Locked Loop](https://en.wikipedia.org/wiki/Phase-locked_loop) algorithms.\nTo do this I'm going to need some demo code, which I'll keep in this repository.\n\n## Blog posts\n\nI recently [posted](http://zipcpu.com) two articles describing the components\nof a basic [PLL](https://en.wikipedia.org/wiki/Phase-locked_loop), and hence\nthe implementation found in this repository.  These are:\n\n1. [How to build a Numerically Controlled Oscillator (NCO)](http://zipcpu.com/dsp/2017/12/09/nco.html) within an [FPGA](https://en.wikipedia.org/wiki/Field-programmable_gate_array).\n\n2. [The Logic PLL](http://zipcpu.com/dsp/2017/12/14/logic-pll.html) based upon the code in [rtl/sdpll.v](rtl/sdpll.v).\n\nIf the [Lord is\nwilling](https://www.blueletterbible.org/kjv/jas/4/15/), I may go deeper\nand describe some other \n[PLL](https://en.wikipedia.org/wiki/Phase-locked_loop) implementations as\nwell--such as the sample time tracking PLL that I recently added.\n\n## Tutorial slides\n\nI placed a quick/short set of [tutorial slides](doc/tutoria.pdf) in the\n[doc/](doc/) directory.  Feel free to browse them and see what you think.\n\n## License\n\nAll of the source code in this repository is released under the\n[GPLv3](https://www.gnu.org/licenses/gpl-3.0.en.html).  If these conditions\nare not sufficient for your needs, other licenses terms may be purchased.\n","funding_links":[],"categories":["Verilog"],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FZipCPU%2Fdpll","html_url":"https://awesome.ecosyste.ms/projects/github.com%2FZipCPU%2Fdpll","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FZipCPU%2Fdpll/lists"}