{"id":13996093,"url":"https://github.com/ZipCPU/fftdemo","last_synced_at":"2025-07-22T23:31:11.849Z","repository":{"id":110285715,"uuid":"141625023","full_name":"ZipCPU/fftdemo","owner":"ZipCPU","description":"A demonstration showing how several components can be compsed to build a simulated spectrogram","archived":false,"fork":false,"pushed_at":"2024-01-19T13:33:34.000Z","size":661,"stargazers_count":35,"open_issues_count":0,"forks_count":9,"subscribers_count":4,"default_branch":"master","last_synced_at":"2024-04-12T09:04:51.058Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/ZipCPU.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null}},"created_at":"2018-07-19T19:57:38.000Z","updated_at":"2024-03-05T23:20:46.000Z","dependencies_parsed_at":"2024-04-12T03:03:08.847Z","dependency_job_id":null,"html_url":"https://github.com/ZipCPU/fftdemo","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/ZipCPU/fftdemo","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Ffftdemo","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Ffftdemo/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Ffftdemo/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Ffftdemo/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/ZipCPU","download_url":"https://codeload.github.com/ZipCPU/fftdemo/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Ffftdemo/sbom","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":266590066,"owners_count":23952860,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","status":"online","status_checked_at":"2025-07-22T02:00:09.085Z","response_time":66,"last_error":null,"robots_txt_status":null,"robots_txt_updated_at":null,"robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-09T14:03:48.648Z","updated_at":"2025-07-22T23:31:11.323Z","avatar_url":"https://github.com/ZipCPU.png","language":"Verilog","readme":"This project contains a Verilator FFT to screen spectrogram demonstration.\nTo build, type \"make\" in the main directory.  This will build a file\n\"main\\_tb\" in the [bench/cpp](bench/cpp) directory, and similarly a\n\"ddr\\_tb\" in the [bench/cpp](bench/cpp) directory.  Running either program\nwill simulate the entire design, all the way from A/D to display output,\nall using Verilator.  The \"main\\_tb\" demo uses an unreasonable amount of\nblock RAM with a VGA output, and the \"ddr\\_tb\" demo uses an external\nDDR3 SDRAM together with a (simulated) HDMI output.\nYou will need to install Verilator and gtkmm to do this.\n\nThere's a pictoral overview of the project in the doc directory\n[here](doc/fftdemo.png), showing all of the components of this design.\nMost of those components can also be seen in the [top-level](rtl/main.v)\nsimulatable file, as a processing flow that works its way through that file.\nListed separately, these components are:\n\n1. A/D, 1Msps, taken from the [wbpmic](https://github.com/ZipCPU/wbpmic) repository\n2. A [filter](rtl/subfiledown.v), taking the A/D input at 1MHz down by a factor of 23x to 40kHz.  A different configuration of this core will reduce the A/D from 1MHz down to 8kHz, for better resolution of speech.\n3. [A hanning window function](rtl/fft/windowfn.v), drawn from the [dblclockfft](https://github.com/ZipCPU/dblclockfft) repository, that not only applies the hanning window but also creates an FFT overlap of 50%\n4. An [FFT](rtl/fft), of 1k points which should therefore yield about 43Hz resolution from a 40kHz stream.\n6. [A very-rudimentary conversion to dB](rtl/fft/logfn.v)\n7. A [controller to write the incoming data to screen memory](rtl/wrdata.v)\n8. [Read from screen memory](rtl/vgasim/imgfifo.v)\n9. [False colormap](rtl/colormap.v)\n10. ... and the final component, the display.  Since this is a verilator simulation, the actual display code, either for [VGA](bench/cpp/vgasim.cpp) or [HDMI](bench/cpp/hdmisim.cpp), is written in C++.  The [VGA simulation code](bench/cpp/vgasim.cpp) was also borrowed, this time from the [vgasim](https://github.com/ZipCPU/vgasim) repository\n\nThis project is in response to all of those students who keep asking how to do\nthis on [Digilent's forum(s)](https://forum.digilentinc.com), while believing\nthat it is impossible to simulate their designs.  In particular, this design\ncan be completely simulated from A/D to video output.  VCD files can be\ngenerated, which will tell you *every trace* within this design--useful for\ndebugging.  Many of the design components have also been formally verified,\nso include several of the FFT components.\n\n## Hardware\n\nThe code now contains an actual hardware implementation.  This implementation\nruns on a Nexys Video board with a PMod MIC3.  It uses the DDR3 SDRAM of the\nNexys Video board for storing the video frames and the HDMI for output.\n\nThis portion of the design is currently working on my desktop.\n\n## Copyright\n\nThis project is shared under the GPLv3 license.  Please feel free to contact\nme if that license is insufficient for your needs.\n","funding_links":[],"categories":["Verilog"],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FZipCPU%2Ffftdemo","html_url":"https://awesome.ecosyste.ms/projects/github.com%2FZipCPU%2Ffftdemo","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FZipCPU%2Ffftdemo/lists"}