{"id":13649348,"url":"https://github.com/ZipCPU/qspiflash","last_synced_at":"2025-04-22T14:31:27.767Z","repository":{"id":110286060,"uuid":"158776833","full_name":"ZipCPU/qspiflash","owner":"ZipCPU","description":"A set of Wishbone Controlled SPI Flash Controllers","archived":false,"fork":false,"pushed_at":"2022-10-31T00:44:25.000Z","size":324,"stargazers_count":75,"open_issues_count":2,"forks_count":24,"subscribers_count":11,"default_branch":"master","last_synced_at":"2024-11-10T00:32:59.456Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/ZipCPU.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null}},"created_at":"2018-11-23T03:32:54.000Z","updated_at":"2024-11-05T01:07:11.000Z","dependencies_parsed_at":"2023-04-08T05:48:45.226Z","dependency_job_id":null,"html_url":"https://github.com/ZipCPU/qspiflash","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Fqspiflash","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Fqspiflash/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Fqspiflash/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Fqspiflash/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/ZipCPU","download_url":"https://codeload.github.com/ZipCPU/qspiflash/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":250258958,"owners_count":21401006,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-02T01:04:57.615Z","updated_at":"2025-04-22T14:31:22.759Z","avatar_url":"https://github.com/ZipCPU.png","language":"Verilog","readme":"This repository has been repurposed from the original [QSPI flash core\nrepository](https://opencores.org/project/qspiflash).  Instead of two large\nand monolithic QSPI flash cores for two different types of flash, this\nrepository now contains three cores: a [SPI flash core](rtl/spixpress.v),\na [Dual SPI flash core](rtl/dualflexpress.v), and a\n[Quad SPI flash core](rtl/qflexpress.v) which should be usable across a wider\nrange of SPI flash chips.  Even better, these new controllers use the\nDDR primitive for the SCK line, so they should be able to run twice as fast\nas the older cores.\n\nThe normal [SPI flash core](rtl/spixpress.v) has been\n[blogged about](http://zipcpu.com/blog/2018/08/16/spiflash.html)\non [ZipCPU.com](http://zipcpu.com).\n\n- Each of these cores has been [formally verified](http://zipcpu.com/blog/2017/10/19/formal-intro.html), though not all of them\n  have seen hardware (yet).  [SymbiYosys](https://symbiyosys.readthedocs.io/en/latest) scripts for verification may be found\n  in the [bench/formal](bench/formal) directory, together with\n  [GTKwave](https://gtkwave.sourceforge.net) save files for viewing any\n  resulting traces.\n\n  If you'd like to get a glimpse of how these various cores might work, feel\n  free to run [SymbiYosys](https://symbiyosys.readthedocs.io/en/latest) to generate demonstration cover traces.\n\n- A [flash simulator](bench/cpp/flashsim.cpp) has been placed into the\n  [bench/cpp](bench/cpp) directory.  You may find this useful when simulating\n  any of these flash cores using [Verilator](https://www.veripool.org/wiki/verilator).\n\n- A [software flash driver](sw/flashdrvr.cpp) can be found in the [sw](sw)\n  directory.  You may find this useful for writing values to any of these\n  flash controllers.  This driver has seen some simulation testing, but it has\n  not (yet) been completed.\n\n- [AutoFPGA scripts](autodata/) have been created for each flash device, though\n  not yet tested.\n\n## Status\n\nAlthough this project has been around for quite some time, it is currently in\nthe process of getting a massive rewrite.  As of today, the RTL code is\ncomplete although it still needs to see hardware.  The simulation software\nis also full featured, and has been used to simulate many flash devices.\nWork remains integrating the flash controllers into their various designs using\n[AutoFPGA](https://github.com/ZipCPU/autofpga),\nas well as testing the various flash controllers in hardware once integrated.\nThe [software driver code](sw/flashdrvr.cpp) will be used for this test, and will need to be\nfull featured by then for that purpose.\n\nIn some, the following are left to do:\n\n- Write a simulation script to demonstrate each of the respective flash\n  controllers.  This would replace the [old script](bench/cpp/qspiflash_tb.cpp)\n  from before the rewrite.\n\n- Update the [AutoFPGA](https://github.com/ZipCPU/autofpga) scripts to make\n  certain they work with both Xilinx and iCE40 parts.  (Intel parts remain in\n  the distance)\n\n  Currently, the [QSPI flash controller](rtl/qflexpress.v) works nicely in\n  simultion within a different project.\n\n- Update the [software flash driver](sw/flashdrvr.cpp) so that one driver\n  can apply to any controller\n\n- The last remains of the [older driver](rtl/wbqspiflash.v), and [its\n  cousin](rtl/eqspiflash.v) need to be removed from the repository.\n\n- The specification needs some formatting work and editing.\n\n## License\n\nThese three cores, together with their supporting infrastructure, have\nbeen released under the [LGPL license](doc/lgpl-3.0.pdf).  You are welcome\nto use these cores under that license.\n","funding_links":[],"categories":["Verilog"],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FZipCPU%2Fqspiflash","html_url":"https://awesome.ecosyste.ms/projects/github.com%2FZipCPU%2Fqspiflash","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FZipCPU%2Fqspiflash/lists"}