{"id":13996087,"url":"https://github.com/ZipCPU/sdr","last_synced_at":"2025-07-22T23:30:46.847Z","repository":{"id":110286146,"uuid":"238207933","full_name":"ZipCPU/sdr","owner":"ZipCPU","description":"A basic Soft(Gate)ware Defined Radio architecture","archived":false,"fork":false,"pushed_at":"2024-01-18T20:09:59.000Z","size":1108,"stargazers_count":75,"open_issues_count":0,"forks_count":15,"subscribers_count":13,"default_branch":"master","last_synced_at":"2024-11-29T18:43:23.550Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/ZipCPU.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null}},"created_at":"2020-02-04T13:04:50.000Z","updated_at":"2024-11-25T02:51:21.000Z","dependencies_parsed_at":"2024-04-12T03:03:08.459Z","dependency_job_id":null,"html_url":"https://github.com/ZipCPU/sdr","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/ZipCPU/sdr","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Fsdr","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Fsdr/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Fsdr/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Fsdr/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/ZipCPU","download_url":"https://codeload.github.com/ZipCPU/sdr/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Fsdr/sbom","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":266589902,"owners_count":23952832,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","status":"online","status_checked_at":"2025-07-22T02:00:09.085Z","response_time":66,"last_error":null,"robots_txt_status":null,"robots_txt_updated_at":null,"robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-09T14:03:48.380Z","updated_at":"2025-07-22T23:30:46.351Z","avatar_url":"https://github.com/ZipCPU.png","language":"Verilog","readme":"# A Software Defined Radio Project for FPGAs\n\nOkay, so ... FPGA designs aren't really software.  Perhaps this should more\nappropriately be named a \"Gateware Defined Radio\" project--but that spoils the\nidea.\n\nThe goal of this project is to build a gateware design that can transfer audio\nfrom one radio to another.  The design is built around the\n[icebreaker](https://github.com/icebreaker-fpga/icebreaker) FPGA board,\nthe [SX1257 Radio PMod](https://github.com/xil-se/SX1257-PMOD),\nthe [Digilent MEMS microphone](https://store.digilentinc.com/pmod-mic3-mems-microphone-with-adjustable-gain/)\nand the [Digilent AMP2 PMod](https://store.digilentinc.com/pmod-amp2-audio-amplifier/).\nYou can see [a picture of this setup here](doc/radio-set.jpg).\n\n## Building the design\n\nThis repository actually contains several designs.  There's an\n[AM transmitter](rtl/amxmit.v),\nan [FM transmitter](rtl/fmxmit.v),\na [QPSK transmitter](rtl/qpskxmit.v),\nan [AM receiver](rtl/amdemod.v), an\n[FM receiver](rtl/fmdemod.v), and a\n[QPSK receiver](rtl/qpskrcvr.v).  There are also three composed  designs, which\ncompose the transmitter and receiver together for simulation (only) purposes.\nWhich design gets built into the repository\nis controlled by which \"RF\" line in the [AutoFPGA\nMakefile](autodata/Makefile) is uncommented.\n\nTo build, you'll first need [AutoFPGA](https://github.com/ZipCPU/autofpga)\ninstalled and in your path.  You can then run `make autodata` to build the\n[top level design](rtl/toplevel.v), [PCF](rtl/sdr.pcf),\n[simulation](sim/main_tb.cpp), and [software data files](sw/regdefs.h).  From\nhere, `make rtl` will build the design, `make sim` will build the simulator,\nand `make sw` will build the host support software.\n\nBeware, if you use any of the composed simulations, such as the AM transmitter\nfollowed by the AM demodulator, you will run into a problem where the\nmicrophone and the amplifier are both attempting to use the same pins.  The\nsolution is not to build the composed (transmit/receive) design in rtl.\nInstead, run `make rtl-sim` to build the full simulation.\n\n## Running in Simulation\n\nTo run the design in simulation, simply run the `main_tb` file in the `sim/`\ndirectory.  This isn't very useful at present, however, unless you add the\n`-d` switch to turn on VCD file generation.  You can then examine all the\ntraces from within the design.\n\nBe aware, the simulation has no channel model.  Outputs to the\n[SX1257](https://github.com/xil-se/SX1257-PMOD)\nare simply fed back into the simulation receiver.\n\n## Running on hardware\n\nTo run the design on an icebreaker, you can load the design via\n`sudo iceprog rtl/sdr.bin`.  Once you do that, you'll want to then run\n`sw/netuart /dev/ttyUSB?` (replace with your serial port device).  At this\npoint, you can interact with your design using `wbregs`.  Perhaps more\nimportantly, you can interact with the registers on the\n[SX1257](https://github.com/xil-se/SX1257-PMOD)\nusing the `rfregs`.  In particular, `txconfig.sh` will turn the transmitter\non, and set it up at 915MHz.\n\n## Debugging within hardware\n\nThis design offers two methods for debugging: capturing traces, and capturing\nhistograms from within the data flow.  Two bits of the GPIO register (three\nfor the TX/RX composed simulations) control a tap point selection within the\ndesign.  This tap point contains a CE signal, 32'bits of data, and 10 bits\nof data for a histogram.\n\nTo record a trace from wtihin the hardware, map the signals you wish to capture\nto a Wishbone Scope C++ file--such as [this one for the\nmicrophone](sw/micscope.cpp).  You can then use `wbregs rfscope 0` to reset\nthe scope any time you want to make a new capture, and\n[micscope](sw/micscope.cpp) to extract the captured dasta and then to turn\nit into a VCD file you can then analyze with GTKWave.\n\nAlternatively, you can capture histograms from within the design.  These\ncan be read with the [histogram](sw/histogram.cpp) program.  This program will\nalso output a binary file of 32-bit integers containing your histogram.\n(The\n[histogram](https://zipcpu.com/dsp/2019/12/21/histogram.html)\nis currently hardcoded at 1024 words, due to hardware limitations\nin the iCE40 up5k.)\n\nWith a little creativity, the [histogram capture\nutility](https://zipcpu.com/dsp/2019/12/21/histogram.html) can be turned into\na constellation capture utility.  By sending 5-bits of I and 5-bits of Q\ninto the histogram, and then interpreting the results accordingly, you can\ncapture (and then plot) a constellation diagram.  This is the purpose of\nthe [constellation](sw/constellation.cpp) program.\n\n## Project Status\n\nAs of 20200204, ...\n\n1. The AM receiver works when composed with the transmitter in simulation.\n\tThe simulation has no channel model, is only so good, etc., etc.\n\tIt's a start.\n2. Both FM transmit/receive pair work when composed together in simulation.\n3. The AM transmitter works, and the results can be heard using a Lime\n\tSDR radio receiver.  There's an annoying tone present which I haven't\n\tyet chased down.\n\nAs of 20200727, there's now a [QPSK transmitter](rtl/qpskxmit.v) and\n[receiver](rtl/qpskrcvr.v) which both (roughly) work in simulation.  I say\nroughly because the carrier tracking loop breaks lock even in simulation.\nFurther, the filters used in these designs are horrible block average types\nof filters.  Hence, while the design can recover the incoming audio, there's\nstill lots of room for improvement.\n\n## License\n\nThis project and all of its files are licensed under the GNU General\nPublic License, v3.\n","funding_links":[],"categories":["Verilog"],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FZipCPU%2Fsdr","html_url":"https://awesome.ecosyste.ms/projects/github.com%2FZipCPU%2Fsdr","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FZipCPU%2Fsdr/lists"}