{"id":13649374,"url":"https://github.com/ZipCPU/vgasim","last_synced_at":"2025-04-22T14:31:32.279Z","repository":{"id":110286203,"uuid":"115555467","full_name":"ZipCPU/vgasim","owner":"ZipCPU","description":"A Video display simulator","archived":false,"fork":false,"pushed_at":"2024-07-20T23:57:17.000Z","size":4045,"stargazers_count":155,"open_issues_count":1,"forks_count":19,"subscribers_count":15,"default_branch":"master","last_synced_at":"2024-11-10T00:33:01.547Z","etag":null,"topics":["fpga","gplv3","gtkmm","verilator","verilog","vga","video","video-simulator"],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/ZipCPU.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2017-12-27T20:33:58.000Z","updated_at":"2024-09-21T16:46:21.000Z","dependencies_parsed_at":"2024-01-14T11:00:20.801Z","dependency_job_id":"929119de-2ee4-475b-a47d-2aba53bcb8a5","html_url":"https://github.com/ZipCPU/vgasim","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Fvgasim","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Fvgasim/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Fvgasim/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Fvgasim/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/ZipCPU","download_url":"https://codeload.github.com/ZipCPU/vgasim/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":250258973,"owners_count":21401014,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["fpga","gplv3","gtkmm","verilator","verilog","vga","video","video-simulator"],"created_at":"2024-08-02T01:04:58.463Z","updated_at":"2025-04-22T14:31:27.263Z","avatar_url":"https://github.com/ZipCPU.png","language":"Verilog","readme":"## Controller\n\nThis repository contains a couple of [Video Controller](rtl/wbvgaframe.v)s.\n\nThe original [Video Controller](rtl/wbvgaframe.v)\nincludes not only the [low-level framer](rtl/llvga.v), but also\na [bus controller](rtl/imgfifo.v) to read values from memory to then be\ndisplayed on the screen.  This is the basis of a frame buffer approach to\nvideo.  This capability is fully demonstrated via the [Verilator\nbased](http://zipcpu.com/blog/2017/06/21/looking-at-verilator.html) simulator.\n\nThere are now also two AXI-based cores.  The first is an [AXI-based Video\nController](rtl/axivideo.v) that can produce either VGA or HDMI signals.  This\ncontroller is demonstrated via a [slightly different\nsimulator](bench/cpp/axi_tb.cpp), including simulations for both\n[VGA](bench/cpp/vgasim.cpp) and [HDMI](bench/cpp/hdmisim.cpp).\nThe [second AXI-based video controller will record incoming video signals to\nmemory](rtl/axicamera.v).  The incoming capability is [demonstrated via\na simulation](bench/rtl/axirepeater.v) to capture a piece of your screen via\nan [HDMI source simulator](bench/cpp/hdmisource.cpp), [write it to an AXI-based\nblock RAM frame buffer memory](rtl/axivcamera.v), and then to [read it back out\nagain](rtl/axivdisplay.v) to feed a GTK++ window.\n\n## Simulation\n\nThis repository also contains two basic [video simulator](bench/cpp/vgasim.cpp)\ncomponents.  The first, either [VGASIM](bench/cpp/vgasim.cpp)\nor [HDMISIM](bench/cpp/hdmisim.cpp) takes video outputs from a\nVerilated [design module](bench/rtl/demo.v) and displays them on your screen\nas though it were the monitor the design was displaying to, and the\n[second](bench/cpp/vgasource.cpp) takes a piece of your screen and creates\neither [a VGA source signal](bench/cpp/vgasource.cpp) or [an HDMI source\nsignal](bench/cpp/hdmisource.cpp) with it.\n\nAll [video modes](bench/cpp/videomode.h)\nare supported by simply creating the [simulator object](bench/cpp/vgasim.cpp)\nwith the appropriate mode lines, although the [memory initialization\nfile](bench/cpp/slide.hex) for the [outgoing demo](bench/rtl/demo.v) is\nspecifically formatted for a 1280x1024 screen.\nThe [simulator](bench/cpp/vgasim.cpp) will then create a window of that size\non any GTK enabled screen (i.e. Linux), displaying whatever image [your\ndesign](rtl/wbvgaframe.v) is producing.\n\nThe repository also contains a [test pattern generator](rtl/vgatestsrc.v)\nmodeled roughly after a standard VGA pattern, although not quite the same.  As\nmentioned above, there's also a frame buffered approach to drawing on the window\ncentered around a [wishbone enabled memory driver](rtl/imgfifo.v).  This\nsecond capability will draw a more arbitrary image on the display.\n\nReferences to VGA within this module could just as easily refer to any display.\nBe careful that you match the proper polarity of the sync pulses.\n\n## Building\n\nThere is a [master Makefile](Makefile) in this directory.  Hence, to build\nthis project you should be able to just clone it,\n`git clone https://github.com/ZipCPU/vgasim`, run `make` in the main\ndirectory, and then run one of the test programs, such as `main_tb`, from\nwithin the `bench/cpp` directory.  For those that display images from the\nframe buffer, such as `main_tb` or `axi_tb`, be sure to wait long enough\nto see the outgoing image from the frame buffer--it takes a few seconds.\n\nThe project depends upon having both Verilator and gtkmm-3.0 installed.\n\n## License\n\nAll of the source code in this repository is released under the\n[GPLv3](https://www.gnu.org/licenses/gpl-3.0.en.html).  If these conditions\nare not sufficient for your needs, other licenses terms may be purchased.\n\n","funding_links":[],"categories":["Verilog"],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FZipCPU%2Fvgasim","html_url":"https://awesome.ecosyste.ms/projects/github.com%2FZipCPU%2Fvgasim","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FZipCPU%2Fvgasim/lists"}