{"id":13649308,"url":"https://github.com/ZipCPU/wbsata","last_synced_at":"2025-04-22T14:31:19.531Z","repository":{"id":217099600,"uuid":"616446696","full_name":"ZipCPU/wbsata","owner":"ZipCPU","description":"Wishbone SATA Controller","archived":false,"fork":false,"pushed_at":"2025-03-20T18:19:08.000Z","size":1107,"stargazers_count":13,"open_issues_count":0,"forks_count":1,"subscribers_count":2,"default_branch":"master","last_synced_at":"2025-03-20T19:53:26.860Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"gpl-3.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/ZipCPU.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2023-03-20T12:08:00.000Z","updated_at":"2025-03-17T20:11:06.000Z","dependencies_parsed_at":null,"dependency_job_id":"6e8229ef-e3f8-4806-99ae-d413aa80d10a","html_url":"https://github.com/ZipCPU/wbsata","commit_stats":null,"previous_names":["zipcpu/wbsata"],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Fwbsata","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Fwbsata/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Fwbsata/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Fwbsata/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/ZipCPU","download_url":"https://codeload.github.com/ZipCPU/wbsata/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":250258932,"owners_count":21401000,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-02T01:04:56.341Z","updated_at":"2025-04-22T14:31:14.523Z","avatar_url":"https://github.com/ZipCPU.png","language":"Verilog","readme":"## Wishbone SATA Host Controller\n\nSeveral projects of mine require a WB SATA controller.  The [10Gb Ethernet\nswitch](https://github.com/ZipCPU/eth10g) project is an example of one of these\nprojects.  This repository is intended to be a common IP repository shared by\nthose projects, and encapsulating the test bench(es) specific to the SATA\ncontroller.\n\nA couple quick features of this controller:\n\n1. Since the [ZipCPU](https://github.com/ZipCPU/zipcpu) that will control\n   this IP is big-endian, this controller will need to handle both\n   little-endian commands (per spec) and big-endian data.\n\n   There will be an option to be make the IP fully little-endian.\n\n2. My initial goal will be Gen1 (1500Mb/s) compliance.  Later versions may\n   move on to Gen2 or Gen3 compliance.\n\n## Hardware\n\nMy test setup is (at present) an [Enclustra\nMercury+ST1](https://www.enclustra.com/en/products/base-boards/mercury-st1/)\nboard with an [Enclustra Kintex-7\n160T](https://www.enclustra.com/en/products/fpga-modules/mercury-kx2/)\ndaughter board, connected to an\n[Ospero FPGA Drive FMC](https://opsero.com/product/fpga-drive-fmc-dual/).\n\n## Status\n\nWhile fully funded, this project is currently a\n[work in progress](doc/prjstatus.png).  It is not (yet) fully drafted.  At\npresent it needs three significant capabilities before it can move to\nsimulation (or hardware) testing:\n\n1. A means of issuing and detecting out-of-band signaling: COMINIT, COMRESET,\n   and COMWAKE.\n\n   Yes, the Xilinx GTX transceiver can handle these, however the\n   logic isn't yet present within the IP to handle the control signals to\n   either generate (on TX) or handle (on RX) these various signals.\n\n2. A simulation model.  While I typically use C++ Verilator models, this IP\n   will require a Verilog model to make sure GTX transceiver works as\n   expected--to include the verifying that the out-of-band signals are\n   properly detected and handled.\n\n3. A means of debugging in hardware.  I normally do my hardware debugging using\n   a [Wishbone scope](https://github.com/ZipCPU/wbscope).  This is my intention\n   here as well.  However, the\n   [WBSCOPE](https://github.com/ZipCPU/wbscope) can only capture 32-bits per\n   clock cycle.  In this case, I'll either need to expand that to more bits\n   per clock cycle, or I'll need to choose from among the many critical bits\n   within the IP which 32-bits per cycle are the ones I want to capture.  This\n   little bit of engineering hasn't (yet) taken place.  It needs to take place\n   before I can test on the hardware I have.\n\n## License\n\nThe project is currently licensed under GPLv3.  The [ETH10G\nproject](https://github.com/ZipCPU/eth10g) that will use this capability\nwill relicense it under Apache2.\n\n","funding_links":[],"categories":["Verilog"],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FZipCPU%2Fwbsata","html_url":"https://awesome.ecosyste.ms/projects/github.com%2FZipCPU%2Fwbsata","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FZipCPU%2Fwbsata/lists"}