{"id":13649329,"url":"https://github.com/ZipCPU/wbscope","last_synced_at":"2025-04-22T14:31:21.692Z","repository":{"id":110286296,"uuid":"68853966","full_name":"ZipCPU/wbscope","owner":"ZipCPU","description":"A wishbone controlled scope for FPGA's","archived":false,"fork":false,"pushed_at":"2024-01-12T21:15:25.000Z","size":776,"stargazers_count":72,"open_issues_count":0,"forks_count":6,"subscribers_count":9,"default_branch":"master","last_synced_at":"2024-11-10T00:32:56.729Z","etag":null,"topics":["debugging-tools","fpga","verilator","verilog","wishbone","wishbone-bus"],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/ZipCPU.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2016-09-21T20:14:09.000Z","updated_at":"2024-10-24T16:24:52.000Z","dependencies_parsed_at":"2024-01-13T03:37:51.660Z","dependency_job_id":null,"html_url":"https://github.com/ZipCPU/wbscope","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Fwbscope","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Fwbscope/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Fwbscope/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Fwbscope/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/ZipCPU","download_url":"https://codeload.github.com/ZipCPU/wbscope/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":250258937,"owners_count":21401001,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["debugging-tools","fpga","verilator","verilog","wishbone","wishbone-bus"],"created_at":"2024-08-02T01:04:57.130Z","updated_at":"2025-04-22T14:31:16.685Z","avatar_url":"https://github.com/ZipCPU.png","language":"Verilog","readme":"# A Wishbone Controlled Scope for FPGA's\n\nThis is a generic/library routine for providing a bus accessed 'scope' or\n(perhaps more appropriately) a bus accessed logic analyzer for use internal to\nan FPGA.  The general operation is such that this 'scope' can record and report\non any 32 bit value transiting through the FPGA that you have connected to the\nscope.  Once started and reset, the\nscope records a copy of the input data every time the clock ticks with the\ncircuit enabled.  That is, it records these values up until the trigger.  Once\nthe trigger goes high, the scope will record for ``bw_holdoff`` more counts\nbefore stopping.  Values may then be read from the buffer, oldest to most\nrecent.  After reading, the scope may then be reset for another run.\n\nIn general, therefore, operation happens in this fashion:\n\n1. A reset is issued.\n2. Recording starts, in a circular buffer, and continues until\n3. The trigger line is asserted.\n  The scope registers the asserted trigger by setting the ``o_triggered`` output flag.\n4. A counter then ticks until the last value is written.\n  The scope registers that it has stopped recording by setting the ``o_stopped`` output flag.\n5. The scope recording is then paused until the next reset.\n6. While stopped, the CPU can read the data from the scope\n\n  - oldest to most recent\n  - one value per bus clock\n\n7. Writes to the data register reset the address to the beginning of the buffer\n\n# Tutorials\n\nThe Wishbone scope was featured on [zipcpu.com](http://zipcpu.com) as [a\nconclusion](http://zipcpu.com/blog/2017/07/08/getting-started-with-wbscope.html)\nto the discussion of the example [debugging\nbus](https://github.com/ZipCPU/dbgbus/tree/master/hexbus).\nThat example discussed how to hook up the scope to your logic, as well as how\nto employ the [scope software](sw/scopecls.cpp) to create a VCD file\nthat could then be viewed in GTKWave.\nThe scope was also mentioned as a means of capturing [traces of button\nbounces](http://zipcpu.com/blog/2017/08/02/debounce-teaser.html),\nwith the short discussion of how to set it up for that task\n[here](http://zipcpu.com/blog/2017/08/07/bounce-dbgbus.html).\n\n# Interfaces supported\n\n1. [Wishbone B4/pipelined](rtl/wbscope.v)\n2. [AXI lite](rtl/axilscope.v)\n3. [Avalon](rtl/avscope.v)\n4. [Memory backed scope, using AXI](rtl/memscope.v).  This is great for when\n   your data capture can't git in the on-chip RAM of a device.  Using this\n   core, you can store your capture in an off-chip SDRAM.  Beware, an\n   SDRAM can hold a _LOT_ of data.\n5. [_Compressed_ Memory backed scope, using AXI](rtl/memscopc.v).  This uses the\n   same basic run-length compression scheme as the [original compressed\n   Wishbone scope](rtl/wbscopc.v), only this time with the AXI memory\n   back end.\n\n# Commercial Applications\n\nShould you find the GPLv3 license insufficient for your needs, other licenses\ncan be purchased from [Gisselquist Technology,\nLLC](http://zipcpu.com/about/gisselquist-technology.html).\n","funding_links":[],"categories":["Verilog"],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FZipCPU%2Fwbscope","html_url":"https://awesome.ecosyste.ms/projects/github.com%2FZipCPU%2Fwbscope","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FZipCPU%2Fwbscope/lists"}