{"id":13996091,"url":"https://github.com/ZipCPU/zipversa","last_synced_at":"2025-07-22T23:31:08.449Z","repository":{"id":110286385,"uuid":"176623539","full_name":"ZipCPU/zipversa","owner":"ZipCPU","description":"A Versa Board implementation using the AutoFPGA/ZipCPU infrastructure","archived":false,"fork":false,"pushed_at":"2019-11-19T00:10:21.000Z","size":1496,"stargazers_count":13,"open_issues_count":1,"forks_count":3,"subscribers_count":4,"default_branch":"master","last_synced_at":"2024-11-29T19:38:24.223Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":null,"language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/ZipCPU.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null}},"created_at":"2019-03-20T00:55:33.000Z","updated_at":"2023-08-16T14:10:13.000Z","dependencies_parsed_at":"2023-04-08T05:47:45.254Z","dependency_job_id":null,"html_url":"https://github.com/ZipCPU/zipversa","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/ZipCPU/zipversa","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Fzipversa","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Fzipversa/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Fzipversa/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Fzipversa/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/ZipCPU","download_url":"https://codeload.github.com/ZipCPU/zipversa/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ZipCPU%2Fzipversa/sbom","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":266590046,"owners_count":23952858,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","status":"online","status_checked_at":"2025-07-22T02:00:09.085Z","response_time":66,"last_error":null,"robots_txt_status":null,"robots_txt_updated_at":null,"robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-09T14:03:48.572Z","updated_at":"2025-07-22T23:31:07.575Z","avatar_url":"https://github.com/ZipCPU.png","language":"Verilog","readme":"## Accelerator Architecture Demonstration\n\nThis repository contains a demonstration of an accelerator architecture.  The\narchitecture is built around and to support the [ECP5 Versa board](https://www.latticestore.com/products/tabid/417/categoryid/59/productid/22434/default.aspx).\nIt contains support for one Gb Ethernet interface, Flash, a block RAM device,\nand an internal FFT.  The [ffttest](sw/host/ffttest.cpp) program can be used\nto send FFT data to the design, which will be received by the [fftmain](sw/rv32/fftmain.c) RISC-V program, and sent to the internal accelerator.  Once the\nFFT has been accomplished, the data will be returned back to the host that\nrequested the processing.\n\nAs of this posting, all of these components now work to include the FFT\naccelerator itself.\n\nThe design does not (yet) have support for either the second network port,\nthe PCIe connector, or the SDRAM on board.\n\n## Pre-Requisites\n\nTo build this design, you will need to first install:\n\n- [RISC-V GNU toolchain](https://github.com/riscv/riscv-gnu-toolchain), to include binutils, GCC, and newlib support\n- [Yosys](https://github.com/YosysHQ/yosys)\n- [Project Trellis](https://github.com/SymbiFlow/prjtrellis)\n- [NextPNR](https://github.com/YosysHQ/nextpnr) for the ECP5\n- [Verilator](https://www.veripool.org/wiki/verilator)\n- [AutoFPGA](https://github.com/ZipCPU/autofpga)\n- [libELF](https://sourceware.org/elfutils)\n- [NCurses](https://invisible-island.net/ncurses)\n- [OpenOCD](https://openocd.org)\n\n## Build\n\nTo adjust the peripherals attached to the design, run `make autodata`.  (This\nis not necessary in general.)\n\nThen, to build the design, run `make` from the main directory.\n\nTo load the design onto the device once it has been built, run\n\n```bash\n% openocd -f ecp5-versa.cfg -c \"transport select jtag; init; svf rtl/zipversa.svf; exit\"\n```\n\nYou may need to use sudo to run this command.\n\nOnce the design has been loaded onto the board, you may then load software\non the board using `zipload`, such as:\n\n```bash\n% cd sw/host\n% zipload ../rv32/fftmain\n```\n\nYou can also interact with the board using the software in the `sw/host`\ndirectory.  For example, to run the FFT demo, run:\n\n```bash\n% ./testfft\n```\n\n## License\n\nThis project is licensed under the GPL.\n\n","funding_links":[],"categories":["Verilog"],"sub_categories":[],"project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FZipCPU%2Fzipversa","html_url":"https://awesome.ecosyste.ms/projects/github.com%2FZipCPU%2Fzipversa","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2FZipCPU%2Fzipversa/lists"}