{"id":16117535,"url":"https://github.com/a0u/riscv-isa-sim","last_synced_at":"2025-04-06T09:23:37.494Z","repository":{"id":7696983,"uuid":"9061213","full_name":"a0u/riscv-isa-sim","owner":"a0u","description":"RISC-V Functional ISA Simulator","archived":false,"fork":false,"pushed_at":"2015-01-05T21:27:58.000Z","size":864,"stargazers_count":1,"open_issues_count":0,"forks_count":0,"subscribers_count":2,"default_branch":"master","last_synced_at":"2025-02-12T14:56:37.473Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"","language":"C","has_issues":false,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"other","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/a0u.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null}},"created_at":"2013-03-27T18:52:59.000Z","updated_at":"2016-05-15T16:20:31.000Z","dependencies_parsed_at":"2022-09-14T21:40:49.282Z","dependency_job_id":null,"html_url":"https://github.com/a0u/riscv-isa-sim","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/a0u%2Friscv-isa-sim","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/a0u%2Friscv-isa-sim/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/a0u%2Friscv-isa-sim/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/a0u%2Friscv-isa-sim/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/a0u","download_url":"https://codeload.github.com/a0u/riscv-isa-sim/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":247459303,"owners_count":20942189,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-10-09T20:45:27.873Z","updated_at":"2025-04-06T09:23:37.465Z","avatar_url":"https://github.com/a0u.png","language":"C","funding_links":[],"categories":[],"sub_categories":[],"readme":"RISC-V ISA Simulator\n======================\n\nAuthor  : Andrew Waterman, Yunsup Lee\n\nDate    : June 19, 2011\n\nVersion : (under version control)\n\nAbout\n-------------\n\nThe RISC-V ISA Simulator implements a functional model of one or more\nRISC-V processors.\n\nBuild Steps\n---------------\n\nWe assume that the RISCV environment variable is set to the RISC-V tools\ninstall path, and that the riscv-fesvr package is installed there.\n\n    $ mkdir build\n    $ cd build\n    $ ../configure --prefix=$RISCV --with-fesvr=$RISCV\n    $ make\n    $ [sudo] make install\n\nCompiling and Running a Simple C Program\n-------------------------------------------\n\nInstall spike (see Build Steps), riscv-gnu-toolchain, and riscv-pk.\n\nWrite a short C program and name it hello.c.  Then, compile it into a RISC-V\nELF binary named hello:\n\n    $ riscv64-unknown-elf-gcc -o hello hello.c\n\nNow you can simulate the program atop the proxy kernel:\n\n    $ spike pk hello\n\nSimulating a New Instruction\n------------------------------------\n\nAdding an instruction to the simulator requires two steps:\n\n  1.  Describe the instruction's functional behavior in the file\n      riscv/insns/\u003cnew_instruction_name\u003e.h.  Examine other instructions\n      in that directory as a starting point.\n\n  2.  Add the opcode and opcode mask to riscv/opcodes.h.  Alternatively,\n      add it to the riscv-opcodes package, and it will do so for you:\n\n         $ cd ../riscv-opcodes\n         $ vi opcodes       // add a line for the new instruction\n         $ make install\n\n  3.  Rebuild the simulator.\n\nInteractive Debug Mode\n---------------------------\n\nTo invoke interactive debug mode, launch spike with -d:\n\n    $ spike -d pk hello\n\nTo see the contents of a register (0 is for core 0):\n\n    : reg 0 a0\n\nTo see the contents of a memory location (physical address in hex):\n\n    : mem 2020\n\nTo see the contents of memory with a virtual address (0 for core 0):\n\n    : mem 0 2020\n\nYou can advance by one instruction by pressing \u003center\u003e. You can also\nexecute until a desired equality is reached:\n\n    : until pc 0 2020                   (stop when pc=2020)\n    : until mem 2020 50a9907311096993   (stop when mem[2020]=50a9907311096993)\n\nAlternatively, you can execute as long as an equality is true:\n\n    : while mem 2020 50a9907311096993\n\nYou can continue execution indefinitely by:\n\n    : r\n\nAt any point during execution (even without -d), you can enter the\ninteractive debug mode with `\u003ccontrol\u003e-\u003cc\u003e`.\n\nTo end the simulation from the debug prompt, press `\u003ccontrol\u003e-\u003cc\u003e` or:\n\n    : q\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fa0u%2Friscv-isa-sim","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fa0u%2Friscv-isa-sim","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fa0u%2Friscv-isa-sim/lists"}