{"id":25053377,"url":"https://github.com/abdallahabusidu/cmp305-introduction-verilog","last_synced_at":"2026-01-07T23:45:17.124Z","repository":{"id":123138694,"uuid":"356021157","full_name":"abdallahabusidu/CMP305-introduction-Verilog","owner":"abdallahabusidu","description":"introduction to Verilog in Integrated Circuit Design And VLSI technology","archived":false,"fork":false,"pushed_at":"2021-04-09T00:02:33.000Z","size":6,"stargazers_count":1,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2025-03-31T06:45:27.872Z","etag":null,"topics":["verilog","verilog-code","verilog-hdl","verilog-project"],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/abdallahabusidu.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2021-04-08T19:06:40.000Z","updated_at":"2021-04-29T19:33:05.000Z","dependencies_parsed_at":null,"dependency_job_id":"e0b02b75-89a2-4630-b32d-40f20b2ee049","html_url":"https://github.com/abdallahabusidu/CMP305-introduction-Verilog","commit_stats":null,"previous_names":["abdallahabusidu/cmp305-introduction-verilog","abdallahabusedo/cmp305-introduction-verilog"],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/abdallahabusidu%2FCMP305-introduction-Verilog","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/abdallahabusidu%2FCMP305-introduction-Verilog/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/abdallahabusidu%2FCMP305-introduction-Verilog/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/abdallahabusidu%2FCMP305-introduction-Verilog/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/abdallahabusidu","download_url":"https://codeload.github.com/abdallahabusidu/CMP305-introduction-Verilog/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":246429447,"owners_count":20775806,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["verilog","verilog-code","verilog-hdl","verilog-project"],"created_at":"2025-02-06T11:27:14.113Z","updated_at":"2026-01-07T23:45:17.071Z","avatar_url":"https://github.com/abdallahabusidu.png","language":"Verilog","funding_links":[],"categories":[],"sub_categories":[],"readme":"# CMP305-introduction-Verilog\nintroduction to Verilog in Integrated Circuit Design And VLSI technology\n\n\n\u003cdiv align=\"center\"\u003e\n  \n# THIS IS A NOTES FOR MYSELF TAKEN FROM THIS VIDEO  [LINK_OF_THE_VIDEO](https://www.youtube.com/watch?v=PJGvZSlsLKs)\n\u003cspan style=\"display:block;text-align:center\"\u003e\n\n# Verilog language \n\u003c/div\u003e\n\n- Standard Hardware description Language (HDL).\n- used to describe a digital system.\n\u003cdiv align=\"center\"\u003e\n\n## Behavior Modeling\n\u003c/div\u003e\n- A Component is described by its I/O response.\n- only the functionality of the circuit no structure.\n\u003cdiv align=\"center\"\u003e\n\n## Structural Modeling \n\u003c/div\u003e\n- A component is described by interconnecting Lower-Level Component/primitives \n- Both Functionality and structure of the circuit \n\u003cdiv align=\"center\"\u003e\n\n## Register Transfer Level (RTL)\n\u003c/div\u003e\n- A type of behavioral modeling for the purpose of synthesis\n### Synthesis : Translating HDL to a circuit and then optimizing the represented circuit\n\u003cdiv align=\"center\"\u003e\n\n# Module declaration \n\u003c/div\u003e\n1) begins with keyword module \n2) provides module name \n3) include port list\n\n```\nmodule multi (\n        // port_list types\n        1- input  =\u003e input port \n        2- output =\u003e output port \n        3- inout  =\u003e bidirectional port \n    \n);\n    // port declaration \n    \"\u003cport_type\u003e \u003cport_name\u003e;\"\n    \n    // data type declatation\n        =\u003e Net Data type \n            -\u003e represents physical interconnect between structures \n        -- wire \n        -- tri \n        -- supply0\n           supply1\n        example\n        wire [7:0] out;\n        tri enable;\n        \n        =\u003e Variable Data type \n            -\u003e represent element to store data temporarily \n        -- reg \n        -- integer\n        -- real\n        -- time\n        -- realtimer\n\n    // instantiation format \n        \u003ccomponent_name\u003e #\u003cdelay\u003e \u003cinstance_name\u003e (port_list);\n        #\u003cdelay\u003e -\u003e delay through component\n        \n    // circuit functionality  \n    // timing specifications \n\nendmodule //multi\n```\n\u003cdiv align=\"center\"\u003e\n\n# Connecting Module Instantiation Ports \n\u003c/div\u003e\n\n#### Two Methods to define ports connections \n## 1) By Ordered list \n- port connections defined by the order of the port list in the lower-level module declaration \n```\nmodule half_adder ( co , sum , a , b ); \n```\n```\nhalf_adder u1 ( c1 , s1 , a , b );\n```\n- the order dose matter \nco -\u003e c1 | sum -\u003e S1 | a -\u003e a | b -\u003e b\n\n## 2) By Name *(RECOMMENDED METHOD)*\n- Port connections defined by name \n- order does not matter \n\n\u003cdiv align=\"center\"\u003e\n\n# Parameters\n\u003c/div\u003e\n\n- Value assigned to a symbolic name \n- must resolve to a constant at compile time \n- can be overwritten at compile time \n- \"localparam\" -\u003e same as parameters but cannot be overwritten\n\nex\n```\nparameters size = 8; // can be overwritten \nlocalparam outsize = 16; //can't be overwritten\n```\n\u003chr\u003e\n\u003cdiv align=\"center\"\u003e\n\n# Numbers\n\u003c/div\u003e\n\n1) Sized -\u003e 3'b010 = 3bits wide binary number\n    - 3 indicated the size of number \n\n2) Unsized -\u003e 123 = 32bit decimal number \n\n### Base Formats\n\n- Decimal (d || D ) =\u003e 16'd255\n- Hexadecimal (h || H) =\u003e 8'h9a\n- Binary (b || B) =\u003e b1010\n- Octal (o || O) =\u003e o21\n- Signed (s || S) 16'shFA\n\n### Negative numbers \n\n- legal ==\u003e -8'd3\n- illegal ==\u003e 4'd-2 ERROR\n\n### Special Number Characters\n\n- underlined ( _ ) used for readability \n    - 32'h21_65_bc_fe\n- X or x unknown value \n    - 12'h12x\n- z or Z high impedance value \n    - 1'bz \n\u003chr\u003e\n\u003cdiv align=\"center\"\u003e\n\n# Arithmetic operators  \n\u003c/div\u003e\n\u003cpre\u003e\nain =5 ; bin =10 ; cin =2'b01; din =2'b0z\n1) \"+\" =\u003e Add      |  bin+cin =\u003e 11\n2) \"-\" =\u003e Subtract |  bin-cin =\u003e 9\n3) \"*\" =\u003e Multiply |  ain*bin =\u003e 50\n4) \"/\" =\u003e Divide   |  bin/ain =\u003e 2\n5) \"%\" =\u003e Modulus  |  bin%ain =\u003e 0\n6) \"**\"=\u003e Exponent |  ain**2  =\u003e 25\n\u003c/pre\u003e\n\u003cdiv align=\"center\"\u003e\n\n# Bitwise operators  \n\u003c/div\u003e\n\u003cpre\u003e\n1) \"~\" =\u003e  | invert each bit  \n2) \"\u0026\" =\u003e  | And \n3) \"|\" =\u003e  | OR\n4) \"^\" =\u003e  | XOR \n5) \"^~\" =\u003e | XNOR\n\u003c/pre\u003e\n\u003cdiv align=\"center\"\u003e\n\n# Reduction operators  \n\u003c/div\u003e\n\u003cpre\u003e\n1) \"\u0026\" =\u003e          | AND  \n2) \"~\u0026\" =\u003e         | NAND \n3) \"|\" =\u003e          | OR\n4) \"~|\" =\u003e         | NOR \n5) \"^\" =\u003e          | XOR\n6) \"~^\" or \"^~\" =\u003e | XNOR\n\u003c/pre\u003e\n\u003cdiv align=\"center\"\u003e\n\n# Relational operators  \n\u003c/div\u003e\n\u003cpre\u003e\n1) \"\u003e\" =\u003e  | Grater than  \n2) \"\u003c\" =\u003e  | Less than\n3) \"\u003e=\" =\u003e | Greater than or equal\n4) \"\u003c=\" =\u003e | Less than or equal\n\u003c/pre\u003e\n\u003cdiv align=\"center\"\u003e\n\n# Equality operators  \n\u003c/div\u003e\n\u003cpre\u003e\n1) \"==\" =\u003e  | Equality\n2) \"!=\" =\u003e  | inEquality\n3) \"===\" =\u003e | Case Equality\n4) \"!==\" =\u003e | Case inEquality\n\u003c/pre\u003e\n\u003cdiv align=\"center\"\u003e\n\n# Logical operators  \n\u003c/div\u003e\n\u003cpre\u003e\n1) \"!\" =\u003e  | Not\n2) \"\u0026\u0026\" =\u003e | AND \n3) \"||\" =\u003e | OR\n\u003c/pre\u003e\n\u003cdiv align=\"center\"\u003e\n\n# Shift operators  \n\u003c/div\u003e\n\u003cpre\u003e\n1) \"\u003c\u003c\" =\u003e  | logical shift left\n2) \"\u003e\u003e\" =\u003e  | logical shift right\n3) \"\u003c\u003c\u003c\" =\u003e | Arithmetic shift left\n3) \"\u003e\u003e\u003e\" =\u003e | Arithmetic shift right\n\u003c/pre\u003e\n\u003cdiv align=\"center\"\u003e\n\n# Miscellaneous operators  \n\u003c/div\u003e\n\u003cpre\u003e\n1) \"?:\" =\u003e   | Conditional test\n2) \"{}\" =\u003e   | Concatenate\n3) \"{{}}\" =\u003e | Replicate\n\u003c/pre\u003e\n\u003chr\u003e\n\u003cdiv align=\"center\"\u003e\n\n# Making Assignments\n\u003c/div\u003e\n\n## 1) Continuous Assignment Statement\n```\nwire[15:0] adder_out =mult_out + out;\n```\nequivalent to \n```\nwire[15:0] adder_out;\nassign adder_out = mult_out + out;\n```\nwhen the RHS changes , expression is evaluated and LHS net is updated immediately.\n\n## 2) Procedural Assignment Blocks\n* Initial =\u003e used to initialized behavioral statements for simulation \n    * start at time 0 \n    * execute only once during simulation then does not execute again \n    * statements inside execute sequentially \n    * Keywords begin and end must be used if block contains more than one statement\n    * Examples \n        * Initialization \n        * Monitoring \n        * any functionality that needs to be turned on just once \n* Always =\u003e used to describe te circuit functionality using behavioral statements\n    * Blocks execute concurrently \n    * start at time 0 \n    * and continuously in a looping fashion \n    * Behavioral statements inside an initial block execute sequentially\n    * Examples \n        * Modeling a digital circuit\n        * any Process or functionality needs to be executed continuously \n\n- each one represent a separate process \n- each consists of behavioral statements\n\nExample on Always and initial statements \n\n```\nmodule clk_gen\n    #(parameters period =50)\n(\n    output reg clk\n);\n    initial clk = 1'b0;\n\n    always \n        #(period/2)clk =~clk;\n    \n    initial #100 $finish;\n\nendmodule\n```\n\n## Two Types of Procedural Assignments \n\n1) Blocking Assignments = \n    - executed in the order they are specified in the seq. way \n\nExample a=1 b=2\n```\ninitial \n    begin \n        a = #5 b ;\n        c = #10 a;\n    end\n``` \n\n\u003cpre\u003e\n|\n|   a=b=2       c=a=2\n|_____|_____|_____|_____|_\n0     5     10    15    20\n\u003c/pre\u003e\n\n2) Nonblocking Assignments \u003c=\n    - allow scheduling of assignments without blocking execution of the statements that follow in a seq block\n\nExample a=1 b=2\n```\ninitial \n    begin \n        a \u003c= #5 b ;\n        c \u003c= #10 a;\n    end\n```\n\u003cpre\u003e\n|\n|   a=b=2  c=a=1\n|_____|_____|_____|_____|_\n0     5     10    15    20\n\u003c/pre\u003e\n\n- = for combinatorial logic\n- \u003c= for sequential logic \n\u003chr\u003e\n\u003cdiv align=\"center\"\u003e\n\n# Tow types of RTL processes\n\u003c/div\u003e\n\n1) Combinatorial Processes\n-   sensitive to all inputs used in the Combinatorial logic\n\n```\nalways @(a,b,sel)\nalways @* \n```\n2) Clocked Processes\n-   sensitive to clock or/and control signals \n\n```\nalways @(Posedge clk , negedge clr_n)\n```\n\u003chr\u003e\n\n\u003cdiv align=\"center\"\u003e\n\n# Behavioral Statements\n\u003c/div\u003e\n\n1) if-else \n```\nalways @* begin\nif(s)\n    q=a;\nelse if(sb)\n    q=b;\nelse\n    q=c;\nend\n```\n2) case\n ```\nalways @* begin\ncase(s)\n    2'b00 : q = a;\n    2'b01 : q = b;\n    2'b10 : q = c;\n    default : q =d;\nendcase\nend\n```\n3) Loop\n    - forever loop \n    ```\n    initial begin \n        clk=0\n        forever #25 clk =~clk;\n    end\n    ```\n    - repeat loopp\n    ```\n    if(rotate ==1)\n        repeat (8) begin\n            tmp= data[15];\n            data={data\u003c\u003c 1 ,tmp};\n        end\n    ```\n    - while loop\n    ```\n    initial begin \n        count =0;\n        while (count \u003c 101) begin \n            count = count+1;\n        end\n    end\n    ```\n    - for loop \n    ```\n    integer i;\n    always @(inp, cnt) begin \n        result[7:4]=0;\n        result[3:0]=inp;\n        if(cnt==1) begin\n            for(i=4; i\u003c= 7 ; i=i+1) begin\n                result[i]=result[i-4];\n            end\n            result[3:0]=0;\n        end\n    end\n    ```\n\u003chr\u003e\n\n\u003cdiv align=\"center\"\u003e\n\n# Function and Tasks\n\u003c/div\u003e\n\n1) Function \n    - return one value\n    - produces combinatorial logic\n    - used in expressions\n    ```assign mult_out = mult(ina,inb); ```\n\n\n2) Tasks\n    - can return multi values\n    - can be combinatorial or registered\n    - task are invoked as statement \n    ```stm_out(nxt,first,sel,filter); ```\n\nthere are more some differences between Function and Task \ngo and watch the video for more info and examples \n\nthanks for reading \n\nyou are legend 😎","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fabdallahabusidu%2Fcmp305-introduction-verilog","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fabdallahabusidu%2Fcmp305-introduction-verilog","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fabdallahabusidu%2Fcmp305-introduction-verilog/lists"}