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It allows you to load assembly code from a file, run it, and see the results in a GUI.\n\n## Features\n\n- Load assembly code from a file\n- Run the loaded code\n- Step through the code one line at a time\n- View the state of the CPU registers and RAM\n- View the output of the code\n\n## Instruction Set\n\nThe simulator supports the following instructions:\n\n- LOM: Load the data from the memory address into the ACC register. Format: `LOM \u003caddress\u003e`\n- OUT: Output the value in the ACC register. Format: `OUT`\n- STO: Store the data from the ACC register to the memory address. Format: `STO \u003caddress\u003e`\n- ADD: Add the data from the memory address to the ACC register. Format: `ADD \u003caddress\u003e`\n- SUB: Subtract the data from the ACC register. Format: `SUB \u003caddress\u003e`\n- MUL: Multiply the ACC register by the data from the memory address. Format: `MUL \u003caddress\u003e`\n- INR: Increment the register specified by the AR register. Format: `INR`\n- INP: Load the value from the INPR register into the ACC register. Format: `INP`\n- AND: Perform a bitwise AND operation on the ACC register and the data from the memory address. Format: `AND \u003caddress\u003e`\n- OR: Perform a bitwise OR operation on the ACC register and the data from the memory address. Format: `OR \u003caddress\u003e`\n- XOR: Perform a bitwise XOR operation on the ACC register and the data from the memory address. Format: `XOR \u003caddress\u003e`\n- NOT: Perform a bitwise NOT operation on the ACC register. Format: `NOT`\n- JUM: Jump to the memory address specified by the AR register. Format: `JUM \u003caddress\u003e`\n- JUZ: Jump to the memory address specified by the AR register if the ACC register is zero. Format: `JUZ \u003caddress\u003e`\n- FIN: Finish the program execution. Format: `FIN`\n\nIn the above formats, `\u003caddress\u003e` represents the memory address to be used by the instruction.\n\n## Registers\n\nThe simulator uses the following registers:\n\n- ACC: Accumulator register\n- PC: Program counter\n- IR: Instruction register\n- DR: Data register\n- CTR: Counter register\n- OUTR: Output register\n- AR: Address register\n- INPR: Input register\n\n## Usage\n\n1. Clone the repository to your local machine.\n2. Run `simulator.exe` from `dist/`to start the simulator or run the `simulator.py` file in any python supported IDE (ensure both the `simulator.py` and `interpreter.py` are in the same project).\n3. Click the \"Load Code File\" button to load assembly code from a file.\n4. Click the \"Run\" button to run the loaded code.\n5. Click the \"Step\" button to step through the code one line at a time.\n\n## Dependencies\n\n- Python 3.10\n- Tkinter\n\n## Contributing\n\nPull requests are welcome. For major changes, please open an issue first to discuss what you would like to change.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fabdullahimtiazyousafzai%2Fassembly-language-simulator","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fabdullahimtiazyousafzai%2Fassembly-language-simulator","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fabdullahimtiazyousafzai%2Fassembly-language-simulator/lists"}