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logo](docs/fletcher_notext.svg)\n\n# Fletcher: A framework to integrate FPGA accelerators with Apache Arrow\n\n[![Inactively Maintained](https://img.shields.io/badge/Maintenance%20Level-Inactively%20Maintained-yellowgreen.svg)](https://gist.github.com/cheerfulstoic/d107229326a01ff0f333a1d3476e068d)\n[![License](https://badgen.net/github/license/abs-tudelft/fletcher)](https://github.com/abs-tudelft/fletcher/blob/develop/LICENSE)\n[![Last Commit](https://badgen.net/github/last-commit/abs-tudelft/fletcher/develop)](https://badgen.net/github/last-commit/abs-tudelft/fletcher/develop)\n\nFletcher is a framework that helps to integrate FPGA accelerators with tools and\nframeworks that use Apache Arrow in their back-ends.\n\n[Apache Arrow](https://arrow.apache.org/) specifies an in-memory format\ntargeting large datasets and provides libraries for various languages to\ninterface with the data in that format. Arrow prevents the need for\nserialization between different language run-times and provides zero-copy\ninter-process communication of datasets. Languages that have Arrow libraries\n(under development) include C, C++, Go, Java, JavaScript, Python, Ruby and Rust.\n\nWhile many software projects can benefit from these advantages, hardware\naccelerated applications have also seen serious serialization bottlenecks.\nFletcher focuses on FPGA accelerators. Through Fletcher and Arrow, interfacing\n_efficiently_ between FPGA accelerator and high-level language runtimes is made\navailable to all the supported languages.\n\nGiven a set of Arrow\n[Schemas](https://arrow.apache.org/docs/format/Columnar.html), Fletcher\ngenerates the following:\n\n- A **high-performance, easy-to-use hardware interface** for your accelerator\n  kernel:\n  - You provide a range indices of your Arrow RecordBatch (rather than byte\n    address).\n  - You receive (or supply) streams of the data-type specified by the schema\n    (rather than bus words).\n  - No pointer arithmetic, reordering, buffering, etc.. required - Fletcher\n    does this for you, with high throughput (think system bandwidth).\n- A **template** for the accelerator kernel (to be implemented manually or\n  using high-level synthesis)\n  - You connect directly to **streams** of data from/to your RecordBatch rather\n    than some memory bus interface.\n\n![Fletcher overview](fletcher.svg)\n\n## Apache Arrow support\n\n- Fletcher currently supports reading/writing from/to multiple Arrow\n  RecordBatches with an Arrow Schema created from any (nested) combination of:\n\n  - Fixed-width primitives (ints, float, etc...)\n  - Lists (strings, vectors, etc...)\n  - Structs\n  - Validity bitmaps\n\n- In the future we would like to support:\n  - Sparse and dense unions\n  - Dictionaries\n  - Chunked tabular structures (`Arrow::Table`)\n\n## Platform support\n\n- Fletcher is **vendor-agnostic**. Our core hardware descriptions and\n  generated code are vendor independent; we don't use any vendor IP.\n- You can simulate a Fletcher based design without a specific target platform.\n- Tested simulators include the free and open-source\n  [GHDL](https://github.com/ghdl/ghdl) and the proprietary Mentor Graphics\n  Questa/Modelsim, and Xilinx Vivado XSIM.\n\n- The following platforms are (partially) supported (may be work-in-progress):\n  - [Amazon EC2 F1](https://github.com/abs-tudelft/fletcher-aws)\n  - [Xilinx Alveo](https://github.com/abs-tudelft/fletcher-alveo)\n  - [Intel OPAE](https://github.com/abs-tudelft/fletcher-opae)\n  - [OpenPOWER CAPI SNAP](https://github.com/abs-tudelft/fletcher-snap)\n  - [OpenPOWER OpenCAPI OC-Accel](https://github.com/abs-tudelft/fletcher-oc-accel)\n  - Our top-level can be generated to speak AXI, so it should be easy to\n    integrate with many existing systems. Requirements for a platform are that\n    it provides:\n    - An AXI4 (full) interface to memory holding Arrow data structures to\n      operate on (data path), and\n    - An AXI4-lite interface for MMIO to (control path) registers.\n\n## Current state\n\nOur framework is functional, but experimental. \n\n#### ⚠️ This project is currently not actively worked on. ⚠️\n\nEspecially the development branch (which is currently our main branch) may break\nwithout notice. Some larger examples and the supported platforms are quite hard\nto integrate in a CI pipeline (they would take multiple days to complete and\nwould incur significant costs for platforms such as Amazon's EC F1). For now,\nthese larger examples and platform support resides in separate repositories\n(shown above) and are tested against a specific tag of this repository.\n\n## Further reading\n\nTutorials:\n\n- [Simple column sum example](examples/sum/README.md) - The \"Hello, World!\"\n  of Fletcher.\n\nHardware design flow:\n\n- [Fletcher Design Generator](codegen/cpp/fletchgen/README.md) - The design\n  generator converts a set of Arrow Schemas\n  to a hardware design and provides templates for your kernel.\n- [Hardware library](hardware) - All Fletcher core hardware components used\n  by the design generator.\n\nSoftware design flow:\n\n- [Host-side run-time libraries](runtime) - Software libraries for run-time\n  support on the host-machine.\n\n## Example projects\n\n- [Simple column sum example](examples/sum/README.md) - The \"Hello, World!\"\n  of Fletcher.\n- [String writer](examples/stringwrite) - Writes at over 10 GB/s to a column\n  of strings.\n- [Primitive map](codegen/test/primmap) - Maps two primitives to two\n  primitives (simulation-only, used in testing).\n- [String reader](codegen/test/stringread) - Reads some strings\n  (simulation-only, used in testing).\n\nExternal projects using Fletcher:\n\n- [Bolson - A JSON-to-Arrow IPC conversion and Pulsar publish tool.](https://github.com/teratide/bolson)\n- [An FPGA-based Parquet-to-Arrow converter](https://github.com/abs-tudelft/fast-p2a)\n- [Tidre - Demo application for the Tidre regular expression accelerator](https://github.com/teratide/tidre-demo)\n- [Wiki search with Alveo - Very rapidly search a Snappy-compressed version of a Wikipedia database dump](https://github.com/abs-tudelft/wiki-search-alveo)\n- [Regular Expression Matching](https://github.com/abs-tudelft/fletcher-example-regexp)\n- [K-Means clustering](https://github.com/abs-tudelft/fletcher-example-kmeans)\n- [Posit BLAS operations](https://github.com/lvandam/posit_blas_hdl)\n- [Posit PairHMM](https://github.com/lvandam/pairhmm_posit_hdl_arrow)\n\n## Publications\n\nIf you used or studied Fletcher, please cite:\n\n- J. Peltenburg, J. van Straten, L. Wijtemans, L. van Leeuwen, Z. Al-Ars, and\n  H.P. Hofstee, Fletcher: A Framework to Efficiently Integrate FPGA Accelerators\n  with Apache Arrow\\*, in 29th International Conference on Field Programmable\n  Logic and Applications (FPL) (2019) pp. 270–277.\n\nAdditional publications:\n\n- J. Peltenburg, J. van Straten, M. Brobbel, H.P. Hofstee, and Z. Al-Ars,\n  Supporting Columnar In-memory Formats on FPGA: The Hardware Design of Fletcher\n  for Apache Arrow\\*, in Applied Reconfigurable Computing, edited by\n  C. Hochberger, B. Nelson, A. Koch, R. Woods, and P. Diniz (Springer\n  International Publishing, Cham, 2019) pp. 32–47\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fabs-tudelft%2Ffletcher","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Fabs-tudelft%2Ffletcher","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Fabs-tudelft%2Ffletcher/lists"}