{"id":17546061,"url":"https://github.com/aletempiac/dlx","last_synced_at":"2026-01-07T06:52:12.545Z","repository":{"id":177258201,"uuid":"152991519","full_name":"aletempiac/dlx","owner":"aletempiac","description":"Digital design and synthesis of a DLX processor in VHDL","archived":false,"fork":false,"pushed_at":"2019-03-17T10:47:10.000Z","size":15099,"stargazers_count":1,"open_issues_count":0,"forks_count":0,"subscribers_count":0,"default_branch":"master","last_synced_at":"2025-02-03T18:01:36.875Z","etag":null,"topics":["alu","dlx","dlx-processor","processor","vhdl"],"latest_commit_sha":null,"homepage":"","language":"VHDL","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"gpl-3.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/aletempiac.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2018-10-14T15:54:40.000Z","updated_at":"2023-05-03T19:58:01.000Z","dependencies_parsed_at":null,"dependency_job_id":"fd44ccb0-1e61-44db-9b94-7df562d65acf","html_url":"https://github.com/aletempiac/dlx","commit_stats":null,"previous_names":["aletempiac/dlx"],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/aletempiac%2Fdlx","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/aletempiac%2Fdlx/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/aletempiac%2Fdlx/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/aletempiac%2Fdlx/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/aletempiac","download_url":"https://codeload.github.com/aletempiac/dlx/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":246145089,"owners_count":20730495,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["alu","dlx","dlx-processor","processor","vhdl"],"created_at":"2024-10-21T01:43:18.470Z","updated_at":"2026-01-07T06:52:12.505Z","avatar_url":"https://github.com/aletempiac.png","language":"VHDL","funding_links":[],"categories":[],"sub_categories":[],"readme":"# DLX processor project\n\n\u003cimg src=\"images/Datapath_Schematic.svg\" alt=\"Schematic\" style=\"float: left; margin-right: 10px;\" /\u003e  \n\nThe project contains all the VHDL code of a processor, see the [report] for further details.\n\n## How to simulate\n\nIn order to simulate the design, you have to compile your DLX assembly, you have a complete list of all the instructions in the [report]. The compiler is called by [assembler.sh] on a file containing the assembly.  \nFor instance in the command line:\n\n```bash\n$ ./assembler.sh BranchPrediction.asm.txt\n```\n\nIt will generate the machine code that will be read by the Instruction Memory at the start of the simulation.  \n\nUse the script [DLX_sim.scr] to compile the design in ModelSim using\n```bash\n$ source DLX_sim.scr\n```\n\n## Synthesis\n\nThe design present in the `Synthesis` folder is fully synthesizable and [DLX.scr] compiles for Synopsys Design Compiler.\n\n### Developers: Alessandro Tempia Calvino, Fausto Chiatante\nPossible improvements in background:\n- Add floating-point units to the design\n- Multi-cycle execution\n\n[report]: Report.pdf\n[assembler.sh]: Simulation/assembler.sh\n[DLX_sim.scr]: Simulation/DLX_sim.scr\n[DLX.scr]: Synthesis/DLX.scr\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Faletempiac%2Fdlx","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Faletempiac%2Fdlx","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Faletempiac%2Fdlx/lists"}