{"id":13408245,"url":"https://github.com/alexforencich/verilog-axi","last_synced_at":"2026-10-19T09:06:55.279Z","repository":{"id":38451711,"uuid":"142810315","full_name":"alexforencich/verilog-axi","owner":"alexforencich","description":"Verilog AXI components for FPGA implementation","archived":false,"fork":false,"pushed_at":"2025-02-27T23:57:56.000Z","size":562,"stargazers_count":2070,"open_issues_count":67,"forks_count":532,"subscribers_count":50,"default_branch":"master","last_synced_at":"2026-06-09T09:31:09.439Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/alexforencich.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"COPYING","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":"AUTHORS","dei":null,"publiccode":null,"codemeta":null,"zenodo":null,"notice":null,"maintainers":null,"copyright":null,"agents":null,"dco":null,"cla":null}},"created_at":"2018-07-30T01:36:26.000Z","updated_at":"2026-06-08T08:26:39.000Z","dependencies_parsed_at":"2024-10-15T00:21:06.383Z","dependency_job_id":"7542d3b0-45ec-4bff-84d9-7300388161c3","html_url":"https://github.com/alexforencich/verilog-axi","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"purl":"pkg:github/alexforencich/verilog-axi","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/alexforencich%2Fverilog-axi","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/alexforencich%2Fverilog-axi/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/alexforencich%2Fverilog-axi/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/alexforencich%2Fverilog-axi/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/alexforencich","download_url":"https://codeload.github.com/alexforencich/verilog-axi/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/alexforencich%2Fverilog-axi/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":344872684,"owners_count":38352878,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-10-03T21:59:58.778Z","status":"online","status_checked_at":"2026-10-19T02:00:06.414Z","response_time":53,"last_error":null,"robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":true,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-07-30T20:00:51.637Z","updated_at":"2026-10-19T09:06:54.316Z","avatar_url":"https://github.com/alexforencich.png","language":"Verilog","funding_links":[],"categories":["Projects and IPs","Verilog"],"sub_categories":["Communication Technology"],"readme":"# Verilog AXI Components Readme\n\n[![Build Status](https://github.com/alexforencich/verilog-axi/workflows/Regression%20Tests/badge.svg?branch=master)](https://github.com/alexforencich/verilog-axi/actions/)\n\nFor more information and updates: http://alexforencich.com/wiki/en/verilog/axi/start\n\nGitHub repository: https://github.com/alexforencich/verilog-axi\n\n## Deprecation Notice\n\nThis repository is superseded by https://github.com/fpganinja/taxi.  All new features and bug fixes will be applied there, and commercial support is also available.  As a result, this repo is deprecated and will not receive any future maintenance or support.\n\n## Introduction\n\nCollection of AXI4 and AXI4 lite bus components.  Most components are fully\nparametrizable in interface widths.  Includes full cocotb testbenches that\nutilize [cocotbext-axi](https://github.com/alexforencich/cocotbext-axi).\n\n## Documentation\n\n### `axi_adapter` module\n\nAXI width adapter module with parametrizable data and address interface widths.\nSupports INCR burst types and narrow bursts.  Wrapper for `axi_adapter_rd` and `axi_adapter_wr`.\n\n### `axi_adapter_rd` module\n\nAXI width adapter module with parametrizable data and address interface widths.\nSupports INCR burst types and narrow bursts.\n\n### `axi_adapter_wr` module\n\nAXI width adapter module with parametrizable data and address interface widths.\nSupports INCR burst types and narrow bursts.\n\n### `axi_axil_adapter` module\n\nAXI to AXI lite converter and width adapter module with parametrizable data\nand address interface widths.  Supports INCR burst types and narrow bursts.\nWrapper for `axi_axil_adapter_rd` and `axi_axil_adapter_wr`.\n\n### `axi_axil_adapter_rd` module\n\nAXI to AXI lite converter and width adapter module with parametrizable data\nand address interface widths.  Supports INCR burst types and narrow bursts.\n\n### `axi_axil_adapter_wr` module\n\nAXI to AXI lite converter and width adapter module with parametrizable data\nand address interface widths.  Supports INCR burst types and narrow bursts.\n\n### `axi_cdma` module\n\nAXI to AXI DMA engine with parametrizable data and address interface widths.\nGenerates full-width INCR bursts only, with parametrizable maximum burst\nlength.  Supports unaligned transfers, which can be disabled via parameter\nto save on resource consumption.\n\n### `axi_cdma_desc_mux` module\n\nDescriptor multiplexer/demultiplexer for AXI CDMA module.  Enables sharing the\nAXI CDMA module between multiple request sources, interleaving requests and\ndistributing responses.\n\n### `axi_crossbar` module\n\nAXI nonblocking crossbar interconnect with parametrizable data and address\ninterface widths and master and slave interface counts.  Supports all burst\ntypes.  Fully nonblocking with completely separate read and write paths;\nID-based transaction ordering protection logic; and per-port address decode,\nadmission control, and decode error handling.  Wrapper for `axi_crossbar_rd`\nand `axi_crossbar_wr`.\n\nWrappers can generated with `axi_crossbar_wrap.py`.\n\n### `axi_crossbar_addr` module\n\nAddress decode and admission control module for AXI nonblocking crossbar interconnect.\n\n### `axi_crossbar_rd` module\n\nAXI nonblocking crossbar interconnect with parametrizable data and address\ninterface widths and master and slave interface counts.  Read interface only.\nSupports all burst types.  Fully nonblocking with completely separate read and\nwrite paths; ID-based transaction ordering protection logic; and per-port\naddress decode, admission control, and decode error handling.\n\n### `axi_crossbar_wr` module\n\nAXI nonblocking crossbar interconnect with parametrizable data and address\ninterface widths and master and slave interface counts.  Write interface only.\nSupports all burst types.  Fully nonblocking with completely separate read and\nwrite paths; ID-based transaction ordering protection logic; and per-port\naddress decode, admission control, and decode error handling.\n\n### `axi_dma` module\n\nAXI to AXI stream DMA engine with parametrizable data and address interface\nwidths.  Generates full-width INCR bursts only, with parametrizable maximum\nburst length.  Supports unaligned transfers, which can be disabled via\nparameter to save on resource consumption.  Wrapper for `axi_dma_rd` and\n`axi_dma_wr`.\n\n### `axi_dma_desc_mux` module\n\nDescriptor multiplexer/demultiplexer for AXI DMA module.  Enables sharing the\nAXI DMA module between multiple request sources, interleaving requests and\ndistributing responses.\n\n### `axi_dma_rd` module\n\nAXI to AXI stream DMA engine with parametrizable data and address interface\nwidths.  Generates full-width INCR bursts only, with parametrizable maximum\nburst length.  Supports unaligned transfers, which can be disabled via\nparameter to save on resource consumption.\n\n### `axi_dma_wr` module\n\nAXI stream to AXI DMA engine with parametrizable data and address interface\nwidths.  Generates full-width INCR bursts only, with parametrizable maximum\nburst length.  Supports unaligned transfers, which can be disabled via\nparameter to save on resource consumption.\n\n### `axi_dp_ram` module\n\nAXI dual-port RAM with parametrizable data and address interface widths.\nSupports FIXED and INCR burst types as well as narrow bursts.\n\n### `axi_fifo` module\n\nAXI FIFO with parametrizable data and address interface widths.  Supports all\nburst types.  Optionally can delay the address channel until either the write\ndata is completely shifted into the FIFO or the read data FIFO has enough\ncapacity to fit the whole burst.  Wrapper for `axi_fifo_rd` and `axi_fifo_wr`.\n\n### `axi_fifo_rd` module\n\nAXI FIFO with parametrizable data and address interface widths.  AR and R\nchannels only.  Supports all burst types.  Optionally can delay the address\nchannel until either the read data FIFO is empty or has enough capacity to fit\nthe whole burst.\n\n### `axi_fifo_wr` module\n\nAXI FIFO with parametrizable data and address interface widths.  WR, W, and B\nchannels only.  Supports all burst types.  Optionally can delay the address\nchannel until the write data is shifted completely into the write data FIFO,\nor the current burst completely fills the write data FIFO.\n\n### `axi_interconnect` module\n\nAXI shared interconnect with parametrizable data and address interface\nwidths and master and slave interface counts.  Supports all burst types.\nSmall in area, but does not support concurrent operations.\n\nWrappers can generated with `axi_interconnect_wrap.py`.\n\n### `axi_ram` module\n\nAXI RAM with parametrizable data and address interface widths.  Supports FIXED\nand INCR burst types as well as narrow bursts.\n\n### `axi_ram_rd_if` module\n\nAXI RAM read interface with parametrizable data and address interface widths.\nHandles bursts and presents a simplified internal memory interface.  Supports\nFIXED and INCR burst types as well as narrow bursts.\n\n### `axi_ram_wr_if` module\n\nAXI RAM write interface with parametrizable data and address interface widths.\nHandles bursts and presents a simplified internal memory interface.  Supports\nFIXED and INCR burst types as well as narrow bursts.\n\n### `axi_ram_wr_rd_if` module\n\nAXI RAM read/write interface with parametrizable data and address interface\nwidths.  Handles bursts and presents a simplified internal memory interface.\nSupports FIXED and INCR burst types as well as narrow bursts.  Wrapper for\n`axi_ram_rd_if` and `axi_ram_wr_if`.\n\n### `axi_register` module\n\nAXI register with parametrizable data and address interface widths.  Supports\nall burst types.  Inserts simple buffers or skid buffers into all channels.\nChannel register types can be individually changed or bypassed.  Wrapper for\n`axi_register_rd` and `axi_register_wr`.\n\n### `axi_register_rd` module\n\nAXI register with parametrizable data and address interface widths.  AR and R\nchannels only.  Supports all burst types.  Inserts simple buffers or skid\nbuffers into all channels.  Channel register types can be individually changed\nor bypassed.\n\n### `axi_register_wr` module\n\nAXI register with parametrizable data and address interface widths.  WR, W,\nand B channels only.  Supports all burst types.  Inserts simple buffers or\nskid buffers into all channels.  Channel register types can be individually\nchanged or bypassed.\n\n### `axil_adapter` module\n\nAXI lite width adapter module with parametrizable data and address interface\nwidths.  Wrapper for `axi_adapter_rd` and `axi_adapter_wr`.\n\n### `axil_adapter_rd` module\n\nAXI lite width adapter module with parametrizable data and address interface\nwidths.\n\n### `axil_adapter_wr` module\n\nAXI lite width adapter module with parametrizable data and address interface\nwidths.\n\n### `axil_cdc` module\n\nAXI lite clock domain crossing module with parametrizable data and address\ninterface widths.  Wrapper for `axi_cdc_rd` and `axi_cdc_wr`.\n\n### `axil_cdc_rd` module\n\nAXI lite clock domain crossing module with parametrizable data and address\ninterface widths.\n\n### `axil_cdc_wr` module\n\nAXI lite clock domain crossing module with parametrizable data and address\ninterface widths.\n\n### `axil_crossbar` module\n\nAXI lite nonblocking crossbar interconnect with parametrizable data and address\ninterface widths and master and slave interface counts.  Fully nonblocking\nwith completely separate read and write paths; FIFO-based transaction ordering\nprotection logic; and per-port address decode, admission control, and decode\nerror handling.  Wrapper for `axil_crossbar_rd` and `axil_crossbar_wr`.\n\nWrappers can generated with `axil_crossbar_wrap.py`.\n\n### `axil_crossbar_addr` module\n\nAddress decode and admission control module for AXI lite nonblocking crossbar interconnect.\n\n### `axil_crossbar_rd` module\n\nAXI lite nonblocking crossbar interconnect with parametrizable data and address\ninterface widths and master and slave interface counts.  Read interface only.\nFully nonblocking with completely separate read and write paths; FIFO-based\ntransaction ordering protection logic; and per-port address decode, admission\ncontrol, and decode error handling.\n\n### `axil_crossbar_wr` module\n\nAXI lite nonblocking crossbar interconnect with parametrizable data and address\ninterface widths and master and slave interface counts.  Write interface only.\nFully nonblocking with completely separate read and write paths; FIFO-based\ntransaction ordering protection logic; and per-port address decode, admission\ncontrol, and decode error handling.\n\n### `axil_interconnect` module\n\nAXI lite shared interconnect with parametrizable data and address interface\nwidths and master and slave interface counts.  Small in area, but does not\nsupport concurrent operations.\n\nWrappers can generated with `axil_interconnect_wrap.py`.\n\n### `axil_ram` module\n\nAXI lite RAM with parametrizable data and address interface widths.\n\n### `axil_reg_if` module\n\nAXI lite register interface with parametrizable data and address interface\nwidths.  Can be used to assemble a set of control registers across multiple\nmodules and hierarchy levels without complicated arbitration logic.  Wrapper\nfor `axil_reg_if_rd` and `axil_reg_if_wr`.\n\n### `axil_reg_if_rd` module\n\nAXI lite register interface with parametrizable data and address interface\nwidths.  Read direction only.  Can be used to assemble a set of control\nregisters across multiple modules and hierarchy levels without complicated\narbitration logic.\n\n### `axil_reg_if_wr` module\n\nAXI lite register interface with parametrizable data and address interface\nwidths.  Write direction only.  Can be used to assemble a set of control\nregisters across multiple modules and hierarchy levels without complicated\narbitration logic.\n\n### `axil_register` module\n\nAXI lite register with parametrizable data and address interface widths.\nInserts skid buffers into all channels.  Channel registers can be individually\nbypassed.  Wrapper for `axil_register_rd` and `axil_register_wr`.\n\n### `axil_register_rd` module\n\nAXI lite register with parametrizable data and address interface widths.  AR\nand R channels only.  Inserts simple buffers into all channels.  Channel\nregisters can be individually bypassed.\n\n### `axil_register_wr` module\n\nAXI lite register with parametrizable data and address interface widths.  WR,\nW, and B channels only.  Inserts simple buffers into all channels.  Channel\nregisters can be individually bypassed.\n\n### Common signals\n\n    awid     : Write address ID\n    awaddr   : Write address\n    awlen    : Write burst length\n    awsize   : Write burst size\n    awburst  : Write burst type\n    awlock   : Write locking\n    awcache  : Write cache handling\n    awprot   : Write protection level\n    awqos    : Write QoS setting\n    awregion : Write region\n    awuser   : Write user sideband signal\n    awvalid  : Write address valid\n    awready  : Write address ready (from slave)\n    wdata    : Write data\n    wstrb    : Write data strobe (byte select)\n    wlast    : Write data last transfer in burst\n    wuser    : Write data user sideband signal\n    wvalid   : Write data valid\n    wready   : Write data ready (from slave)\n    bid      : Write response ID\n    bresp    : Write response\n    buser    : Write response user sideband signal\n    bvalid   : Write response valid\n    bready   : Write response ready (from master)\n    arid     : Read address ID\n    araddr   : Read address\n    arlen    : Read burst length\n    arsize   : Read burst size\n    arburst  : Read burst type\n    arlock   : Read locking\n    arcache  : Read cache handling\n    arprot   : Read protection level\n    arqos    : Read QoS setting\n    arregion : Read region\n    aruser   : Read user sideband signal\n    arvalid  : Read address valid\n    arready  : Read address ready (from slave)\n    rid      : Read data ID\n    rdata    : Read data\n    rresp    : Read response\n    rlast    : Read data last transfer in burst\n    ruser    : Read data user sideband signal\n    rvalid   : Read response valid\n    rready   : Read response ready (from master)\n\n### Common parameters\n\n    ADDR_WIDTH           : width of awaddr and araddr signals\n    DATA_WIDTH           : width of wdata and rdata signals\n    STRB_WIDTH           : width of wstrb signal\n    ID_WIDTH             : width of *id signals\n    AWUSER_ENABLE        : enable awuser signal\n    AWUSER_WIDTH         : width of awuser signal\n    WUSER_ENABLE         : enable wuser signal\n    WUSER_WIDTH          : width of wuser signal\n    BUSER_ENABLE         : enable buser signal\n    BUSER_WIDTH          : width of buser signal\n    ARUSER_ENABLE        : enable aruser signal\n    ARUSER_WIDTH         : width of aruser signal\n    RUSER_ENABLE         : enable ruser signal\n    RUSER_WIDTH          : width of ruser signal\n\n### Source Files\n\n    rtl/arbiter.v                   : Parametrizable arbiter\n    rtl/axi_adapter.v               : AXI lite width converter\n    rtl/axi_adapter_rd.v            : AXI lite width converter (read)\n    rtl/axi_adapter_wr.v            : AXI lite width converter (write)\n    rtl/axi_axil_adapter.v          : AXI to AXI lite converter\n    rtl/axi_axil_adapter_rd.v       : AXI to AXI lite converter (read)\n    rtl/axi_axil_adapter_wr.v       : AXI to AXI lite converter (write)\n    rtl/axi_cdma.v                  : AXI central DMA engine\n    rtl/axi_cdma_desc_mux.v         : AXI CDMA descriptor mux\n    rtl/axi_crossbar.v              : AXI nonblocking crossbar interconnect\n    rtl/axi_crossbar_addr.v         : AXI crossbar address module\n    rtl/axi_crossbar_rd.v           : AXI crossbar interconnect (read)\n    rtl/axi_crossbar_wr.v           : AXI crossbar interconnect (write)\n    rtl/axi_dma.v                   : AXI DMA engine\n    rtl/axi_dma_desc_mux.v          : AXI DMA descriptor mux\n    rtl/axi_dma_rd.v                : AXI DMA engine (read)\n    rtl/axi_dma_wr.v                : AXI DMA engine (write)\n    rtl/axi_dp_ram.v                : AXI dual-port RAM\n    rtl/axi_fifo.v                  : AXI FIFO\n    rtl/axi_fifo_rd.v               : AXI FIFO (read)\n    rtl/axi_fifo_wr.v               : AXI FIFO (write)\n    rtl/axi_interconnect.v          : AXI shared interconnect\n    rtl/axi_ram.v                   : AXI RAM\n    rtl/axi_ram_rd_if.v             : AXI RAM read interface\n    rtl/axi_ram_wr_if.v             : AXI RAM write interface\n    rtl/axi_ram_wr_rd_if.v          : AXI RAM read/write interface\n    rtl/axi_register.v              : AXI register\n    rtl/axi_register_rd.v           : AXI register (read)\n    rtl/axi_register_wr.v           : AXI register (write)\n    rtl/axil_adapter.v              : AXI lite width converter\n    rtl/axil_adapter_rd.v           : AXI lite width converter (read)\n    rtl/axil_adapter_wr.v           : AXI lite width converter (write)\n    rtl/axil_cdc.v                  : AXI lite CDC\n    rtl/axil_cdc_rd.v               : AXI lite CDC (read)\n    rtl/axil_cdc_wr.v               : AXI lite CDC (write)\n    rtl/axil_crossbar.v             : AXI lite nonblocking crossbar interconnect\n    rtl/axil_crossbar_addr.v        : AXI lite crossbar address module\n    rtl/axil_crossbar_rd.v          : AXI lite crossbar interconnect (read)\n    rtl/axil_crossbar_wr.v          : AXI lite crossbar interconnect (write)\n    rtl/axil_interconnect.v         : AXI lite shared interconnect\n    rtl/axil_ram.v                  : AXI lite RAM\n    rtl/axil_reg_if.v               : AXI lite register interface\n    rtl/axil_reg_if_rd.v            : AXI lite register interface (read)\n    rtl/axil_reg_if_wr.v            : AXI lite register interface (write)\n    rtl/axil_register.v             : AXI lite register\n    rtl/axil_register_rd.v          : AXI lite register (read)\n    rtl/axil_register_wr.v          : AXI lite register (write)\n    rtl/priority_encoder.v          : Parametrizable priority encoder\n\n### AXI4-Lite Interface Example\n\nWrite\n\n                ___     ___     ___     ___     ___    \n    clk     ___/   \\___/   \\___/   \\___/   \\___/   \\___\n                _______\n    awid    XXXX_ID____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\n                _______\n    awaddr  XXXX_ADDR__XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\n                _______\n    awlen   XXXX_00____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\n                _______\n    awsize  XXXX_0_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\n                _______\n    awburst XXXX_0_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\n                _______\n    awprot  XXXX_PROT__XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\n                _______\n    awvalid ___/       \\_______________________________\n            ___________         _______________________\n    awready            \\_______/\n                _______________\n    wdata   XXXX_DATA__________XXXXXXXXXXXXXXXXXXXXXXXX\n                _______________\n    wstrb   XXXX_STRB__________XXXXXXXXXXXXXXXXXXXXXXXX\n                _______________\n    wvalid  ___/               \\_______________________\n                        _______\n    wready  ___________/       \\_______________________\n                                        _______\n    bid     XXXXXXXXXXXXXXXXXXXXXXXXXXXX_ID____XXXXXXXX\n                                        _______\n    bresp   XXXXXXXXXXXXXXXXXXXXXXXXXXXX_RESP__XXXXXXXX\n                                        _______\n    bvalid  ___________________________/       \\_______\n            ___________________________________________\n    bready\n\n\nRead\n\n                ___     ___     ___     ___     ___    \n    clk     ___/   \\___/   \\___/   \\___/   \\___/   \\___\n                _______\n    arid    XXXX_ID____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\n                _______\n    araddr  XXXX_ADDR__XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\n                _______\n    arlen   XXXX_00____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\n                _______\n    arsize  XXXX_0_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\n                _______\n    arburst XXXX_0_____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\n                _______\n    arprot  XXXX_PROT__XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\n                _______\n    arvalid ___/       \\_______________________________\n            ___________________________________________\n    arready\n                                        _______\n    rid     XXXXXXXXXXXXXXXXXXXXXXXXXXXX_ID____XXXXXXXX\n                                        _______\n    rdata   XXXXXXXXXXXXXXXXXXXXXXXXXXXX_DATA__XXXXXXXX\n                                        _______\n    rresp   XXXXXXXXXXXXXXXXXXXXXXXXXXXX_RESP__XXXXXXXX\n                                        _______\n    rvalid  ___________________________/       \\_______\n            ___________________________________________\n    rready\n\n\n## Testing\n\nRunning the included testbenches requires [cocotb](https://github.com/cocotb/cocotb), [cocotbext-axi](https://github.com/alexforencich/cocotbext-axi), and [Icarus Verilog](http://iverilog.icarus.com/).  The testbenches can be run with pytest directly (requires [cocotb-test](https://github.com/themperek/cocotb-test)), pytest via tox, or via cocotb makefiles.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Falexforencich%2Fverilog-axi","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Falexforencich%2Fverilog-axi","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Falexforencich%2Fverilog-axi/lists"}