{"id":13537259,"url":"https://github.com/alexforencich/verilog-ethernet","last_synced_at":"2025-05-14T04:06:45.216Z","repository":{"id":23517706,"uuid":"26883874","full_name":"alexforencich/verilog-ethernet","owner":"alexforencich","description":"Verilog Ethernet components for FPGA implementation","archived":false,"fork":false,"pushed_at":"2025-02-27T23:50:33.000Z","size":5444,"stargazers_count":2505,"open_issues_count":133,"forks_count":748,"subscribers_count":117,"default_branch":"master","last_synced_at":"2025-04-14T18:57:23.104Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"","language":"Verilog","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/alexforencich.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"COPYING","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":"AUTHORS","dei":null,"publiccode":null,"codemeta":null}},"created_at":"2014-11-19T22:04:53.000Z","updated_at":"2025-04-14T09:55:50.000Z","dependencies_parsed_at":"2024-02-11T03:25:52.284Z","dependency_job_id":"ce8f6496-b224-4920-a250-9655a044383a","html_url":"https://github.com/alexforencich/verilog-ethernet","commit_stats":{"total_commits":1109,"total_committers":2,"mean_commits":554.5,"dds":"0.0018034265103696878","last_synced_commit":"baac5f8d811d43853d59d69957975ead8bbed088"},"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/alexforencich%2Fverilog-ethernet","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/alexforencich%2Fverilog-ethernet/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/alexforencich%2Fverilog-ethernet/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/alexforencich%2Fverilog-ethernet/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/alexforencich","download_url":"https://codeload.github.com/alexforencich/verilog-ethernet/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":254067661,"owners_count":22009233,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2024-08-01T09:00:56.911Z","updated_at":"2025-05-14T04:06:44.949Z","avatar_url":"https://github.com/alexforencich.png","language":"Verilog","funding_links":[],"categories":["Connectivity","Hardware-Implementation-by-Verilog","Verilog","硬件_其他","Applications"],"sub_categories":["网络服务_其他"],"readme":"# Verilog Ethernet Components Readme\n\n[![Build Status](https://github.com/alexforencich/verilog-ethernet/workflows/Regression%20Tests/badge.svg?branch=master)](https://github.com/alexforencich/verilog-ethernet/actions/)\n\nFor more information and updates: http://alexforencich.com/wiki/en/verilog/ethernet/start\n\nGitHub repository: https://github.com/alexforencich/verilog-ethernet\n\n## Deprecation Notice\n\nThis repository is superseded by https://github.com/fpganinja/taxi.  All new features and bug fixes will be applied there, and commercial support is also available.  As a result, this repo is deprecated and will not receive any future maintenance or support.\n\n## Introduction\n\nCollection of Ethernet-related components for gigabit, 10G, and 25G packet\nprocessing (8 bit and 64 bit datapaths).  Includes modules for handling\nEthernet frames as well as IP, UDP, and ARP and the components for\nconstructing a complete UDP/IP stack.  Includes MAC modules for gigabit and\n10G/25G, a 10G/25G PCS/PMA PHY module, and a 10G/25G combination MAC/PCS/PMA\nmodule.  Includes various PTP related components for implementing systems that\nrequire precise time synchronization.  Also includes full cocotb testbenches\nthat utilize [cocotbext-eth](https://github.com/alexforencich/cocotbext-eth).\n\nFor IP and ARP support only, use `ip_complete` (1G) or `ip_complete_64`\n(10G/25G).\n\nFor UDP, IP, and ARP support, use `udp_complete` (1G) or `udp_complete_64`\n(10G/25G).\n\nTop level gigabit and 10G/25G MAC modules are `eth_mac_*`, with various\ninterfaces and with/without FIFOs.  Top level 10G/25G PCS/PMA PHY module is\n`eth_phy_10g`.  Top level 10G/25G MAC/PCS/PMA combination module is\n`eth_mac_phy_10g`.\n\nPTP components include a configurable PTP clock (`ptp_clock`), a PTP clock CDC\nmodule (`ptp_clock_cdc`) for transferring PTP time across clock domains, and a\nconfigurable PTP period output module for precisely generating arbitrary\nfrequencies from PTP time.\n\nExample designs implementing a simple UDP echo server are included for the\nfollowing boards:\n\n*  Alpha Data ADM-PCIE-9V3 (Xilinx Virtex UltraScale+ XCVU3P)\n*  BittWare 520N-MX (Intel Stratix 10 MX 1SM21CHU2F53E2VG)\n*  Digilent Arty A7 (Xilinx Artix 7 XC7A35T)\n*  Digilent Atlys (Xilinx Spartan 6 XC6SLX45)\n*  Intel Cyclone 10 LP (Intel Cyclone 10 10CL025YU256I7G)\n*  Terasic DE2-115 (Intel Cyclone IV E EP4CE115F29C7)\n*  Terasic DE5-Net (Intel Stratix V 5SGXEA7N2F45C2)\n*  Exablaze ExaNIC X10 (Xilinx Kintex UltraScale XCKU035)\n*  Exablaze ExaNIC X25 (Xilinx Kintex UltraScale+ XCKU3P)\n*  HiTech Global HTG-9200 (Xilinx Virtex UltraScale+ XCVU9P)\n*  HiTech Global HTG-640 (HTG-V6HXT-100GIG-565) (Xilinx Virtex 6 XC6VHX565T)\n*  Silicom fb2CG@KU15P (Xilinx Kintex UltraScale+ XCKU15P)\n*  Xilinx KC705 (Xilinx Kintex 7 XC7K325T)\n*  Xilinx ML605 (Xilinx Virtex 6 XC6VLX240T)\n*  NetFPGA SUME (Xilinx Virtex 7 XC7V690T)\n*  Digilent Nexys Video (Xilinx Artix 7 XC7A200T)\n*  Intel Stratix 10 DX dev kit (Intel Stratix 10 DX 1SD280PT2F55E1VG)\n*  Intel Stratix 10 MX dev kit (Intel Stratix 10 MX 1SM21CHU1F53E1VG)\n*  Xilinx Alveo U50 (Xilinx Virtex UltraScale+ XCU50)\n*  Xilinx Alveo U55C (Xilinx Virtex UltraScale+ XCU55C)\n*  Xilinx Alveo U55N/Varium C1100 (Xilinx Virtex UltraScale+ XCU55N)\n*  Xilinx Alveo U200 (Xilinx Virtex UltraScale+ XCU200)\n*  Xilinx Alveo U250 (Xilinx Virtex UltraScale+ XCU250)\n*  Xilinx Alveo U280 (Xilinx Virtex UltraScale+ XCU280)\n*  Xilinx VCU108 (Xilinx Virtex UltraScale XCVU095)\n*  Xilinx VCU118 (Xilinx Virtex UltraScale+ XCVU9P)\n*  Xilinx VCU1525 (Xilinx Virtex UltraScale+ XCVU9P)\n*  Xilinx ZCU102 (Xilinx Zynq UltraScale+ XCZU9EG)\n*  Xilinx ZCU106 (Xilinx Zynq UltraScale+ XCZU7EV)\n*  Arista 7132LB-48Y4C (Xilinx Virtex UltraScale+ XCVU9P)\n\n## Documentation\n\n### `arp` module\n\nARP handling logic with parametrizable retry timeout parameters and\nparametrizable datapath.\n\n### `arp_cache` module\n\nBasic hash-based cache for ARP entries.  Parametrizable depth.  \n\n### `arp_eth_rx` module\n\nARP frame receiver with parametrizable datapath.\n\n### `arp_eth_tx` module\n\nARP frame transmitter with parametrizable datapath.\n\n### `axis_eth_fcs` module\n\nEthernet frame check sequence calculator.\n\n### `axis_eth_fcs_64` module\n\nEthernet frame check sequence calculator with 64 bit datapath for 10G/25G\nEthernet.\n\n### `axis_eth_fcs_check` module\n\nEthernet frame check sequence checker.\n\n### `axis_eth_fcs_insert` module\n\nEthernet frame check sequence inserter.\n\n### `axis_gmii_rx` module\n\nAXI stream GMII/MII frame receiver with clock enable and MII select.\n\n### `axis_gmii_tx` module\n\nAXI stream GMII/MII frame transmitter with clock enable and MII select.\n\n### `axis_xgmii_rx_32` module\n\nAXI stream XGMII frame receiver with 32 bit datapath.\n\n### `axis_xgmii_rx_64` module\n\nAXI stream XGMII frame receiver with 64 bit datapath.\n\n### `axis_xgmii_tx_32` module\n\nAXI stream XGMII frame transmitter with 32 bit datapath.\n\n### `axis_xgmii_tx_64` module\n\nAXI stream XGMII frame transmitter with 64 bit datapath.\n\n### `eth_arb_mux` module\n\nEthernet frame arbitrated multiplexer with parametrizable data width and port\ncount.  Supports priority and round-robin arbitration.\n\n### `eth_axis_rx` module\n\nEthernet frame receiver with parametrizable datapath.\n\n### `eth_axis_tx` module\n\nEthernet frame transmitter with parametrizable datapath.\n\n### `eth_demux` module\n\nEthernet frame demultiplexer with parametrizable data width and port count.\nSupports priority and round-robin arbitration.\n\n### `eth_mac_1g` module\n\nGigabit Ethernet MAC with GMII interface.\n\n### `eth_mac_1g_fifo` module\n\nGigabit Ethernet MAC with GMII interface and FIFOs.\n\n### `eth_mac_1g_gmii` module\n\nTri-mode Ethernet MAC with GMII/MII interface and automatic PHY rate\nadaptation logic.\n\n### `eth_mac_1g_gmii_fifo` module\n\nTri-mode Ethernet MAC with GMII/MII interface, FIFOs, and automatic PHY rate\nadaptation logic.\n\n### `eth_mac_1g_rgmii` module\n\nTri-mode Ethernet MAC with RGMII interface and automatic PHY rate adaptation\nlogic.\n\n### `eth_mac_1g_rgmii_fifo` module\n\nTri-mode Ethernet MAC with RGMII interface, FIFOs, and automatic PHY rate\nadaptation logic.\n\n### `eth_mac_10g` module\n\n10G/25G Ethernet MAC with XGMII interface.  Datapath selectable between 32 and\n64 bits.\n\n### `eth_mac_10g_fifo` module\n\n10G/25G Ethernet MAC with XGMII interface and FIFOs.  Datapath selectable\nbetween 32 and 64 bits.\n\n### `eth_mac_mii` module\n\nEthernet MAC with MII interface.\n\n### `eth_mac_mii_fifo` module\n\nEthernet MAC with MII interface and FIFOs.\n\n### `eth_mac_phy_10g` module\n\n10G/25G Ethernet MAC/PHY combination module with SERDES interface.\n\n### `eth_mac_phy_10g_fifo` module\n\n10G/25G Ethernet MAC/PHY combination module with SERDES interface and FIFOs.\n\n### `eth_mac_phy_10g_rx` module\n\n10G/25G Ethernet MAC/PHY combination module with SERDES interface, RX path.\n\n### `eth_mac_phy_10g_tx` module\n\n10G/25G Ethernet MAC/PHY combination module with SERDES interface, TX path.\n\n### `eth_mux` module\n\nEthernet frame multiplexer with parametrizable data width and port count.\nSupports priority and round-robin arbitration.\n\n### `eth_phy_10g` module\n\n10G/25G Ethernet PCS/PMA PHY.\n\n### `eth_phy_10g_rx` module\n\n10G/25G Ethernet PCS/PMA PHY receive-side logic.\n\n### `eth_phy_10g_rx_ber_mon` module\n\n10G/25G Ethernet PCS/PMA PHY BER monitor.\n\n### `eth_phy_10g_rx_frame_sync` module\n\n10G/25G Ethernet PCS/PMA PHY frame synchronizer.\n\n### `eth_phy_10g_tx` module\n\n10G/25G Ethernet PCS/PMA PHY transmit-side logic.\n\n### `gmii_phy_if` module\n\nGMII/MII PHY interface and clocking logic.\n\n### `ip` module\n\nIPv4 block with 8 bit data width for gigabit Ethernet.  Manages IPv4 packet\ntransmission and reception.  Interfaces with ARP module for MAC address lookup.\n\n### `ip_64` module\n\nIPv4 block with 64 bit data width for 10G/25G Ethernet.  Manages IPv4 packet\ntransmission and reception.  Interfaces with ARP module for MAC address lookup.\n\n### `ip_arb_mux` module\n\nIP frame arbitrated multiplexer with parametrizable data width and port count.\nSupports priority and round-robin arbitration.\n\n### `ip_complete` module\n\nIPv4 module with ARP integration.\n\nTop level for gigabit IP stack.\n\n### `ip_complete_64` module\n\nIPv4 module with ARP integration and 64 bit data width for 10G/25G Ethernet.\n\nTop level for 10G/25G IP stack.\n\n### `ip_demux` module\n\nIP frame demultiplexer with parametrizable data width and port count.\nSupports priority and round-robin arbitration.\n\n### `ip_eth_rx` module\n\nIP frame receiver.\n\n### `ip_eth_rx_64` module\n\nIP frame receiver with 64 bit datapath for 10G/25G Ethernet.\n\n### `ip_eth_tx` module\n\nIP frame transmitter.\n\n### `ip_eth_tx_64` module\n\nIP frame transmitter with 64 bit datapath for 10G/25G Ethernet.\n\n### `ip_mux` module\n\nIP frame multiplexer with parametrizable data width and port count.\nSupports priority and round-robin arbitration.\n\n### `lfsr` module\n\nFully parametrizable combinatorial parallel LFSR/CRC module.\n\n### `mii_phy_if` module\n\nMII PHY interface and clocking logic.\n\n### `ptp_clock` module\n\nPTP clock module with PPS output.  Generates both 64 bit and 96 bit timestamp\nformats.  Fine frequency adjustment supported with configurable fractional\nnanoseconds field.\n\n### `ptp_clock_cdc` module\n\nPTP clock CDC module with PPS output.  Use this module to transfer and deskew a\nfree-running PTP clock across clock domains.  Supports both 64 and 96 bit\ntimestamp formats.\n\n### `ptp_td_leaf` module\n\nPTP time distribution leaf clock module.  Accepts PTP time distribution messages from the `ptp_td_phc` module, and outputs both the 96-bit time-of-day timestamp and 64-bit relative timestamp in the destination clock domain, as well as both single-cycle and stretched PPS outputs.  Also supports pipelining the serial data input, automatically compensating for the pipeline delay.\n\n### `ptp_td_phc` module\n\nPTP time distribution master clock module.  Generates PTP time distribution messages over a serial interface that can provide PTP time to one or more leaf clocks (`ptp_td_leaf`), as well as both single-cycle and stretched PPS outputs.  The fractional nanoseconds portion is shared between the time-of-day and relative timestamps to support reconstruction of the 96-bit time-of-day timestamp from a truncated relative timestamp.  The module supports coarse setting of both the ToD and relative timestamps as well as atomically applying offsets to the ToD and relative timestamps and the shared fractional nanoseconds.\n\n### `ptp_ts_extract` module\n\nPTP timestamp extract module.  Use this module to extract a PTP timestamp\nembedded in the `tuser` sideband signal of an AXI stream interface.\n\n### `ptp_perout` module\n\nPTP period output module.  Generates a pulse output, configurable in absolute\nstart time, period, and width, based on PTP time from a PTP clock.\n\n### `rgmii_phy_if` module\n\nRGMII PHY interface and clocking logic.\n\n### `udp` module\n\nUDP block with 8 bit data width for gigabit Ethernet.  Manages UDP packet\ntransmission and reception.\n\n### `udp_64` module\n\nUDP block with 64 bit data width for 10G/25G Ethernet.  Manages UDP packet\ntransmission and reception.\n\n### `udp_arb_mux` module\n\nUDP frame arbitrated multiplexer with parametrizable data width and port\ncount.  Supports priority and round-robin arbitration.\n\n### `udp_checksum_gen` module\n\nUDP checksum generator module.  Calculates UDP length, IP length, and\nUDP checksum fields.\n\n### `udp_checksum_gen_64` module\n\nUDP checksum generator module with 64 bit datapath.  Calculates UDP\nlength, IP length, and UDP checksum fields.\n\n### `udp_complete` module\n\nUDP module with IPv4 and ARP integration.\n\nTop level for gigabit UDP stack.\n\n### `udp_complete_64` module\n\nUDP module with IPv4 and ARP integration and 64 bit data width for 10G\nEthernet.\n\nTop level for 10G/25G UDP stack.\n\n### `udp_demux` module\n\nUDP frame demultiplexer with parametrizable data width and port count.\nSupports priority and round-robin arbitration.\n\n### `udp_ip_rx` module\n\nUDP frame receiver.\n\n### `udp_ip_rx_64` module\n\nUDP frame receiver with 64 bit datapath for 10G/25G Ethernet.\n\n### `udp_ip_tx` module\n\nUDP frame transmitter.\n\n### `udp_ip_tx_64` module\n\nUDP frame transmitter with 64 bit datapath for 10G/25G Ethernet.\n\n### `udp_mux` module\n\nUDP frame multiplexer with parametrizable data width and port count.\nSupports priority and round-robin arbitration.\n\n### `xgmii_baser_dec_64` module\n\nXGMII 10GBASE-R decoder for 10G PCS/PMA PHY.\n\n### `xgmii_baser_enc_64` module\n\nXGMII 10GBASE-R encoder for 10G PCS/PMA PHY.\n\n### `xgmii_deinterleave` module\n\nXGMII de-interleaver for interfacing with PHY cores that interleave the\ncontrol and data lines.\n\n### `xgmii_interleave` module\n\nXGMII interleaver for interfacing with PHY cores that interleave the control\nand data lines.\n\n### Common signals\n\n    tdata   : Data (width generally DATA_WIDTH)\n    tkeep   : Data word valid (width generally KEEP_WIDTH, present on _64 modules)\n    tvalid  : Data valid\n    tready  : Sink ready\n    tlast   : End-of-frame\n    tuser   : Bad frame (valid with tlast \u0026 tvalid)\n\n### Source Files\n\n    rtl/arp.v                       : ARP handling logic\n    rtl/arp_cache.v                 : ARP LRU cache\n    rtl/arp_eth_rx.v                : ARP frame receiver\n    rtl/arp_eth_tx.v                : ARP frame transmitter\n    rtl/eth_arb_mux.py              : Ethernet frame arbitrated multiplexer generator\n    rtl/axis_eth_fcs.v              : Ethernet FCS calculator\n    rtl/axis_eth_fcs_64.v           : Ethernet FCS calculator (64 bit)\n    rtl/axis_eth_fcs_insert.v       : Ethernet FCS inserter\n    rtl/axis_eth_fcs_check.v        : Ethernet FCS checker\n    rtl/axis_gmii_rx.v              : AXI stream GMII/MII receiver\n    rtl/axis_gmii_tx.v              : AXI stream GMII/MII transmitter\n    rtl/axis_xgmii_rx_32.v          : AXI stream XGMII receiver (32 bit)\n    rtl/axis_xgmii_rx_64.v          : AXI stream XGMII receiver (64 bit)\n    rtl/axis_xgmii_tx_32.v          : AXI stream XGMII transmitter (32 bit)\n    rtl/axis_xgmii_tx_64.v          : AXI stream XGMII transmitter (64 bit)\n    rtl/eth_arb_mux.v               : Ethernet frame arbitrated multiplexer\n    rtl/eth_axis_rx.v               : Ethernet frame receiver\n    rtl/eth_axis_tx.v               : Ethernet frame transmitter\n    rtl/eth_demux.v                 : Ethernet frame demultiplexer\n    rtl/eth_mac_1g.v                : Gigabit Ethernet GMII MAC\n    rtl/eth_mac_1g_fifo.v           : Gigabit Ethernet GMII MAC with FIFO\n    rtl/eth_mac_1g_gmii.v           : Tri-mode Ethernet GMII/MII MAC\n    rtl/eth_mac_1g_gmii_fifo.v      : Tri-mode Ethernet GMII/MII MAC with FIFO\n    rtl/eth_mac_1g_rgmii.v          : Tri-mode Ethernet RGMII MAC\n    rtl/eth_mac_1g_rgmii_fifo.v     : Tri-mode Ethernet RGMII MAC with FIFO\n    rtl/eth_mac_10g.v               : 10G/25G Ethernet XGMII MAC\n    rtl/eth_mac_10g_fifo.v          : 10G/25G Ethernet XGMII MAC with FIFO\n    rtl/eth_mac_mii.v               : Ethernet MII MAC\n    rtl/eth_mac_mii_fifo.v          : Ethernet MII MAC with FIFO\n    rtl/eth_mac_phy_10g.v           : 10G/25G Ethernet XGMII MAC/PHY\n    rtl/eth_mac_phy_10g_fifo.v      : 10G/25G Ethernet XGMII MAC/PHY with FIFO\n    rtl/eth_mac_phy_10g_rx.v        : 10G/25G Ethernet XGMII MAC/PHY RX with FIFO\n    rtl/eth_mac_phy_10g_tx.v        : 10G/25G Ethernet XGMII MAC/PHY TX with FIFO\n    rtl/eth_mux.v                   : Ethernet frame multiplexer\n    rtl/gmii_phy_if.v               : GMII PHY interface\n    rtl/iddr.v                      : Generic DDR input register\n    rtl/ip.v                        : IPv4 block\n    rtl/ip_64.v                     : IPv4 block (64 bit)\n    rtl/ip_arb_mux.v                : IP frame arbitrated multiplexer\n    rtl/ip_complete.v               : IPv4 stack (IP-ARP integration)\n    rtl/ip_complete_64.v            : IPv4 stack (IP-ARP integration) (64 bit)\n    rtl/ip_demux.v                  : IP frame demultiplexer\n    rtl/ip_eth_rx.v                 : IPv4 frame receiver\n    rtl/ip_eth_rx_64.v              : IPv4 frame receiver (64 bit)\n    rtl/ip_eth_tx.v                 : IPv4 frame transmitter\n    rtl/ip_eth_tx_64.v              : IPv4 frame transmitter (64 bit)\n    rtl/ip_mux.v                    : IP frame multiplexer\n    rtl/lfsr.v                      : Generic LFSR/CRC module\n    rtl/mii_phy_if.v                : MII PHY interface\n    rtl/oddr.v                      : Generic DDR output register\n    rtl/ptp_clock.v                 : PTP clock\n    rtl/ptp_clock_cdc.v             : PTP clock CDC\n    rtl/ptp_td_leaf.v               : PTP time distribution leaf clock\n    rtl/ptp_td_phc.v                : PTP time distribution master clock\n    rtl/ptp_ts_extract.v            : PTP timestamp extract\n    rtl/ptp_perout.v                : PTP period out\n    rtl/rgmii_phy_if.v              : RGMII PHY interface\n    rtl/ssio_ddr_in.v               : Generic source synchronous IO DDR input module\n    rtl/ssio_ddr_in_diff.v          : Generic source synchronous IO DDR differential input module\n    rtl/ssio_ddr_out.v              : Generic source synchronous IO DDR output module\n    rtl/ssio_ddr_out_diff.v         : Generic source synchronous IO DDR differential output module\n    rtl/ssio_sdr_in.v               : Generic source synchronous IO SDR input module\n    rtl/ssio_sdr_in_diff.v          : Generic source synchronous IO SDR differential input module\n    rtl/ssio_sdr_out.v              : Generic source synchronous IO SDR output module\n    rtl/ssio_sdr_out_diff.v         : Generic source synchronous IO SDR differential output module\n    rtl/udp.v                       : UDP block\n    rtl/udp_64.v                    : UDP block (64 bit)\n    rtl/udp_arb_mux.v               : UDP frame arbitrated multiplexer\n    rtl/udp_checksum_gen.v          : UDP checksum generator\n    rtl/udp_checksum_gen_64.v       : UDP checksum generator (64 bit)\n    rtl/udp_complete.v              : UDP stack (IP-ARP-UDP)\n    rtl/udp_complete_64.v           : UDP stack (IP-ARP-UDP) (64 bit)\n    rtl/udp_demux.v                 : UDP frame demultiplexer\n    rtl/udp_ip_rx.v                 : UDP frame receiver\n    rtl/udp_ip_rx_64.v              : UDP frame receiver (64 bit)\n    rtl/udp_ip_tx.v                 : UDP frame transmitter\n    rtl/udp_ip_tx_64.v              : UDP frame transmitter (64 bit)\n    rtl/udp_mux.v                   : UDP frame multiplexer\n    rtl/xgmii_baser_dec_64.v        : XGMII 10GBASE-R decoder\n    rtl/xgmii_baser_enc_64.v        : XGMII 10GBASE-R encoder\n    rtl/xgmii_deinterleave.v        : XGMII data/control de-interleaver\n    rtl/xgmii_interleave.v          : XGMII data/control interleaver\n\n### AXI Stream Interface Example\n\ntransfer with header data\n\n                  __    __    __    __    __    __    __\n    clk        __/  \\__/  \\__/  \\__/  \\__/  \\__/  \\__/  \\__\n               ______________                   ___________\n    hdr_ready                \\_________________/\n                        _____ \n    hdr_valid  ________/     \\_____________________________\n                        _____\n    hdr_data   XXXXXXXXX_HDR_XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\n                        ___________ _____ _____\n    tdata      XXXXXXXXX_A0________X_A1__X_A2__XXXXXXXXXXXX\n                        ___________ _____ _____\n    tkeep      XXXXXXXXX_K0________X_K1__X_K2__XXXXXXXXXXXX\n                        _______________________\n    tvalid     ________/                       \\___________\n                              _________________\n    tready     ______________/                 \\___________\n                                          _____\n    tlast      __________________________/     \\___________\n\n    tuser      ____________________________________________\n\n\ntwo byte transfer with sink pause after each byte\n\n              __    __    __    __    __    __    __    __    __\n    clk    __/  \\__/  \\__/  \\__/  \\__/  \\__/  \\__/  \\__/  \\__/  \\__\n                    _____ _________________\n    tdata  XXXXXXXXX_D0__X_D1______________XXXXXXXXXXXXXXXXXXXXXXXX\n                    _____ _________________\n    tkeep  XXXXXXXXX_K0__X_K1______________XXXXXXXXXXXXXXXXXXXXXXXX\n                    _______________________\n    tvalid ________/                       \\_______________________\n           ______________             _____             ___________\n    tready               \\___________/     \\___________/\n                          _________________\n    tlast  ______________/                 \\_______________________\n\n    tuser  ________________________________________________________\n\n\ntwo back-to-back packets, no pauses\n\n              __    __    __    __    __    __    __    __    __\n    clk    __/  \\__/  \\__/  \\__/  \\__/  \\__/  \\__/  \\__/  \\__/  \\__\n                    _____ _____ _____ _____ _____ _____\n    tdata  XXXXXXXXX_A0__X_A1__X_A2__X_B0__X_B1__X_B2__XXXXXXXXXXXX\n                    _____ _____ _____ _____ _____ _____\n    tkeep  XXXXXXXXX_K0__X_K1__X_K2__X_K0__X_K1__X_K2__XXXXXXXXXXXX\n                    ___________________________________\n    tvalid ________/                                   \\___________\n           ________________________________________________________\n    tready\n                                _____             _____\n    tlast  ____________________/     \\___________/     \\___________\n\n    tuser  ________________________________________________________\n\n\nbad frame\n\n              __    __    __    __    __    __\n    clk    __/  \\__/  \\__/  \\__/  \\__/  \\__/  \\__\n                    _____ _____ _____\n    tdata  XXXXXXXXX_A0__X_A1__X_A2__XXXXXXXXXXXX\n                    _____ _____ _____\n    tkeep  XXXXXXXXX_K0__X_K1__X_K2__XXXXXXXXXXXX\n                    _________________\n    tvalid ________/                 \\___________\n           ______________________________________\n    tready\n                                _____\n    tlast  ____________________/     \\___________\n                                _____\n    tuser  ____________________/     \\___________\n\n\n## Testing\n\nRunning the included testbenches requires [cocotb](https://github.com/cocotb/cocotb), [cocotbext-axi](https://github.com/alexforencich/cocotbext-axi), [cocotbext-eth](https://github.com/alexforencich/cocotbext-eth), and [Icarus Verilog](http://iverilog.icarus.com/).  The testbenches can be run with pytest directly (requires [cocotb-test](https://github.com/themperek/cocotb-test)), pytest via tox, or via cocotb makefiles.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Falexforencich%2Fverilog-ethernet","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Falexforencich%2Fverilog-ethernet","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Falexforencich%2Fverilog-ethernet/lists"}