{"id":23822194,"url":"https://github.com/alexfru/sedicipuv2","last_synced_at":"2026-04-17T09:31:24.354Z","repository":{"id":270591589,"uuid":"909946136","full_name":"alexfru/SediCiPUv2","owner":"alexfru","description":"SediCiPUv2 CPU architecture","archived":false,"fork":false,"pushed_at":"2025-01-01T15:57:04.000Z","size":256,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"master","last_synced_at":"2025-02-22T00:15:00.886Z","etag":null,"topics":["16-bit","7400","assembler","assembly-language","cpu","homebrew-cpu","isa","logisim","logisim-cpu","logisim-evolution","tests","ttl"],"latest_commit_sha":null,"homepage":"","language":"C","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/alexfru.png","metadata":{"files":{"readme":"readme.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2024-12-30T05:58:24.000Z","updated_at":"2025-02-11T06:37:46.000Z","dependencies_parsed_at":"2025-01-01T16:38:11.257Z","dependency_job_id":"8a66e7a3-a059-4476-b3cd-d98973f556bf","html_url":"https://github.com/alexfru/SediCiPUv2","commit_stats":null,"previous_names":["alexfru/sedicipuv2"],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/alexfru%2FSediCiPUv2","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/alexfru%2FSediCiPUv2/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/alexfru%2FSediCiPUv2/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/alexfru%2FSediCiPUv2/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/alexfru","download_url":"https://codeload.github.com/alexfru/SediCiPUv2/tar.gz/refs/heads/master","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":240105469,"owners_count":19748465,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["16-bit","7400","assembler","assembly-language","cpu","homebrew-cpu","isa","logisim","logisim-cpu","logisim-evolution","tests","ttl"],"created_at":"2025-01-02T09:15:02.609Z","updated_at":"2026-04-17T09:31:24.313Z","avatar_url":"https://github.com/alexfru.png","language":"C","funding_links":[],"categories":[],"sub_categories":[],"readme":"# SediCiPU 2: Proof of Concept\n\n![screenshot](poc.png)\n\n\n## Logisim-evolution project\n\nThe proof of concept is implemented as a Logisim-evolution project,\nspecifically, it was implemented and tested using Logisim-evolution v3.8.0.\n\nThe project implements the SediCiPU 2 CPU ([ISA](SediCiPUv2.md),\n[CPU diagram](CpuDiagram.md)) and a minimum of additional circuitry, namely:\na 16KB ROM, a 4MB RAM, a reset button and 6 IRQ-triggering buttons. There's\nalso a 16KB decoder ROM ([decoder ROM signals](DromSignals.md)) that's\nconsidered part of the CPU (the decoder ROM for the mini variant of the ISA\nis significantly smaller, just 2KB).\n\nThe CPU is implemented mostly with Logisim-evolution's library of the 7400\nseries chips. The library is a bit limited, but fairly sufficient for a CPU.\n\n\n## ROMs\n\nLogisim-evolution offers loading binary files into memories as big-endian\nby default. To save some GUI clicking when loading a new ROM file, you can\ngenerate it in the big-endian byte order, despite the CPU being little-\nendian.\n\n\n### Decoder ROM\n\nTo create the decoder ROM you have to compile `mkdrom.c` into a program\nwith your C compiler and run it, something like this:\n\n    $ gcc -std=c99 -O2 -Wall mkdrom.c -o mkdrom\n    $ ./mkdrom -be drom.bin\n\nThe `-be` option makes the output file, `drom.bin`, big-endian.\n\n\n### Test ROM\n\nTo create the test ROM you have to compile `mktesti.c` into a program\nwith your C compiler and run it, something like this:\n\n    $ gcc -std=c99 -O2 -Wall mktesti.c -o mktesti\n    $ ./mktesti -be testi.bin\n\nThe `-be` option makes the output file, `testi.bin`, big-endian.\n\nNote that `mktesti.c` implements a rather crude but functional assembler\nthat emits the test code to the console in a format that is handy for\ndebugging, e.g.:\n\n    ...\n    mktesti.c:1810   1F58  AC48    li16(r3, 200/*00C8*/),\n    mktesti.c:1810   1F5A  AE01\n    mktesti.c:1811   1F5C  B02C    li16(r4, 300/*012C*/),\n    mktesti.c:1811   1F5E  B202\n    mktesti.c:1812   1F60  D600    lurpc(r5, 0),\n    mktesti.c:1813   1F62  9E8F    addi(pc, r5, 14 + 1), // call mul sub; 60000/*EA60*/\n    mktesti.c:1814   1F64  8920    expect_r16(r2, 0xEA60),\n    mktesti.c:1814   1F66  AA2B\n    mktesti.c:1814   1F68  E4FF\n    mktesti.c:1814   1F6A  A860\n    mktesti.c:1814   1F6C  ABD4\n    mktesti.c:1818   1F6E  B80F    j(7), // skip over mul sub\n    mktesti.c:1822   1F70  A800    li(r2, 0),\n    mktesti.c:1823   1F72  A010    li(r0, 16),\n    mktesti.c:1833   1F74  FEE7    add22adc33(),\n    mktesti.c:1834   1F76  FEEF    cadd24(),\n    mktesti.c:1835   1F78  807F    addi(r0, r0, -1),\n    mktesti.c:1836   1F7A  E4FC    jnz(-4),\n    mktesti.c:1839   1F7C  9E80    addi(pc, r5, 0),\n    ...\n\nYou can see there the original assembly code, its line numbers in the source\nfile and addresses and encoded instructions in the middle columns.\n\n\n## Playing with Proof of Concept\n\nYou can start the project simulation and watch the register and memory\nvalues change during test execution. The test completes and passes\nwhen the program counter register, `pc`, reaches the address of the\nlast instruction in `testi.bin`, that is, file size minus 2. If a test\ncheck fails, the CPU enters an infinite loop in the test and the test\nnever completes.\n\nThe reset button resets the CPU, which amounts to disabling external/\nhardware interrupts, setting the `pc` register (as well as `sel0` and\n`sel4`) to 0 and beginning execution from there in the program ROM.\nThis is how you can restart the test.\n\nThere's no convenient way to set `pc` to an arbitrary value. But there's\na usable one... Look at the indicator connected to CPU's `DBG_CLK` output.\nIf it isn't zero, tick the clock one full cycle or two until `DBG_CLK`\nbecomes zero. When it's zero, a new instruction will be fetched next.\nEdit the contents of the ROM at address `pc`/2 (the division is because\nthe ROM is 16-bit). Write two 16-bit hex values to the ROM: 3F80 and then\nthe new `pc` value. This is the `lw pc, (pc + 0)` instruction followed by\nthe address that it will load into `pc`. Now, tick the clock two full\ncycles and observe `pc` change to the desired value. After this you can\nreload the contents of the ROM from a file to undo the editing and\npossibly apply any code corrections you've made.\n\nWhen external/hardware interrupts are enabled (see the LED connected\nto CPU's `DBG_I` output), the CPU can handle IRQs. The test will enable\ninterrupts at some point (near `pc` = `0x06AE`), when it has tested nearly\nenough of the CPU for it to be able to handle interrupts. At that point\nyou can click the IRQ0...5 buttons to trigger interrupt handling.\nObserve how the stack pointer register, `sp`, decrements when entering\nthe ISR and increments when exiting it. The ISR prioritizes the IRQs with\nIRQ5 having the lowest priority and IRQ0 having the highest. If you click\nIRQ0 through IRQ5 buttons in that order, IRQ0 through IRQ5 will be\nhandled serially. If you click IRQ5 through IRQ0 in that order quickly,\nyou may observe that handling of some IRQs is interrupted by handlers of\nhigher priority IRQs. When this happens, `sp` gets decremented to even\nlower values compared to the case when there's just one outstanding IRQ\nto handle.\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Falexfru%2Fsedicipuv2","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Falexfru%2Fsedicipuv2","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Falexfru%2Fsedicipuv2/lists"}