{"id":35019245,"url":"https://github.com/alh477/demodical","last_synced_at":"2026-04-04T06:03:49.439Z","repository":{"id":330185085,"uuid":"1121888563","full_name":"ALH477/DeMoDiCaL","owner":"ALH477","description":" (an acronym derived from Demodulator-Modulator Digital Caliber) is a proprietary, state-of-the-art one-way communication bus engineered by DeMoD LLC","archived":false,"fork":false,"pushed_at":"2025-12-23T18:30:35.000Z","size":33,"stargazers_count":0,"open_issues_count":0,"forks_count":0,"subscribers_count":0,"default_branch":"main","last_synced_at":"2025-12-25T08:29:05.134Z","etag":null,"topics":[],"latest_commit_sha":null,"homepage":"","language":null,"has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"cern-ohl-w-2.0","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/ALH477.png","metadata":{"files":{"readme":"README.markdown","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null,"zenodo":null,"notice":null,"maintainers":null,"copyright":null,"agents":null,"dco":null,"cla":null}},"created_at":"2025-12-23T18:13:40.000Z","updated_at":"2025-12-23T18:30:39.000Z","dependencies_parsed_at":null,"dependency_job_id":null,"html_url":"https://github.com/ALH477/DeMoDiCaL","commit_stats":null,"previous_names":["alh477/demodical"],"tags_count":null,"template":false,"template_full_name":null,"purl":"pkg:github/ALH477/DeMoDiCaL","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ALH477%2FDeMoDiCaL","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ALH477%2FDeMoDiCaL/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ALH477%2FDeMoDiCaL/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ALH477%2FDeMoDiCaL/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/ALH477","download_url":"https://codeload.github.com/ALH477/DeMoDiCaL/tar.gz/refs/heads/main","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/ALH477%2FDeMoDiCaL/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":31389392,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-04-04T04:26:24.776Z","status":"ssl_error","status_checked_at":"2026-04-04T04:23:34.147Z","response_time":60,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":[],"created_at":"2025-12-27T05:40:54.010Z","updated_at":"2026-04-04T06:03:49.434Z","avatar_url":"https://github.com/ALH477.png","language":null,"funding_links":[],"categories":[],"sub_categories":[],"readme":"# DeMoDiCaL (WIP)\n**High-Speed One-Way Optical Communication Bus**  \n© 2025 DeMoD LLC. All rights reserved.\n\n![DeMoDical Conceptual Logo](https://via.placeholder.com/800x400?text=DeMoDical+High-Speed+Unidirectional+Optical+Link)  \n*The DeMoDical represents a proprietary advancement in secure, high-performance data transmission, leveraging FPGA technology for custom modulation in unidirectional optical links.*\n\n## Table of Contents\n- [Overview](#overview)\n- [Key Features](#key-features)\n- [Educational Background](#educational-background)\n- [System Architecture](#system-architecture)\n- [Hardware Requirements](#hardware-requirements)\n- [Software and FPGA Implementation](#software-and-fpga-implementation)\n- [Installation and Setup](#installation-and-setup)\n- [Usage Guide](#usage-guide)\n- [Performance Metrics](#performance-metrics)\n- [Troubleshooting](#troubleshooting)\n- [Intellectual Property and Licensing](#intellectual-property-and-licensing)\n- [Roadmap](#roadmap)\n- [Contact and Support](#contact-and-support)\n- [References and Further Reading](#references-and-further-reading)\n\n## Overview\nThe **DeMoDical** (an acronym derived from **De**modulator-**Mo**dulator **Di**gital **Cal**iber) is a proprietary, state-of-the-art one-way communication bus engineered by DeMoD LLC for applications demanding ultra-high-speed, secure data transfer. This system excels in scenarios where unidirectional communication is critical, such as in secure network gateways (data diodes), real-time data streaming in industrial environments, high-frequency trading platforms, or proprietary sensor networks.\n\nAt its core, the DeMoDical utilizes field-programmable gate array (FPGA) technology to implement a custom digital modulator, enabling flexible data encoding and transmission over optical fibers. Unlike bidirectional protocols like Ethernet or USB, the DeMoDical enforces strict one-way flow, preventing any reverse data leakage and enhancing security in sensitive operations.\n\nThis repository serves as a high-level resource hub, offering detailed documentation, conceptual diagrams, and educational insights into the underlying technologies. While the core hardware description language (HDL) code and proprietary implementations remain confidential to protect DeMoD LLC's intellectual property, the materials here aim to educate users on the principles of high-speed optical communication and inspire innovation in similar domains.\n\n## Key Features\n- **Ultra-High Bandwidth**: Supports up to 100 Gbps raw throughput (configurable from 40 Gbps), achieved through multi-lane serialization/deserialization (SerDes) technology, with effective payload rates of 80–95 Gbps after accounting for overhead.\n- **Strict Unidirectionality**: Physically enforced one-way data flow using transmit-only (TX) optics on the sender and receive-only (RX) on the recipient, ideal for compliance with security standards like those in cybersecurity frameworks (e.g., NIST SP 800-53 for data diodes).\n- **Custom Programmable Modulator**: Proprietary FPGA-based logic allows for tailored encoding schemes, including scrambling for data randomization, forward error correction (FEC) for reliability, and modulation formats like on-off keying (OOK) or pulse-amplitude modulation (PAM4).\n- **Carrier Signal Emulation**: Embedded clock recovery with optional continuous pseudo-random binary sequence (PRBS) or pilot tones to mimic a carrier signal, ensuring robust synchronization without dedicated hardware.\n- **Optical Medium**: Utilizes multimode fiber (MMF) via QSFP28 Active Optical Cables (AOCs) for low-loss, noise-immune transmission over distances up to 100 meters.\n- **Cost-Effectiveness**: Leverages commodity FPGA boards and optics, keeping prototype costs under $3,500 while delivering enterprise-grade performance.\n- **Low Latency**: End-to-end delays under 100 nanoseconds, suitable for time-sensitive applications.\n- **Robustness**: High bit error rate (BER) tolerance (\u003c10⁻¹²) through proprietary error correction, with support for environmental operation from 0–70°C.\n\n## Educational Background\nTo provide a professional and educational foundation, this section explains key concepts underpinning the DeMoDical design. These explanations are intended for engineers, students, and professionals new to high-speed digital communication.\n\n### What is a Unidirectional Communication Bus?\nA unidirectional bus, often implemented as a \"data diode,\" allows data to flow in only one direction. This prevents backflow, making it invaluable for secure systems where information must exit a high-security network without risking ingress (e.g., from a classified to an unclassified zone). Unlike bidirectional links, it uses physical separation—such as TX-only optics—to enforce this, reducing cyber risks.\n\n### FPGA and SerDes Technology\nField-Programmable Gate Arrays (FPGAs) are reconfigurable integrated circuits that allow custom digital logic implementation via HDL like Verilog or VHDL. In the DeMoDical, FPGAs handle the \"custom modulator\" by processing data streams in parallel and serializing them at gigabit speeds.\n\nSerialization/Deserialization (SerDes) transceivers are high-speed interfaces within FPGAs that convert parallel data (e.g., from memory) into serial streams for transmission. Operating at rates like 25 Gbps per lane, they embed clock signals into the data (using encodings like 64B/66B) to eliminate the need for separate clock lines, improving efficiency and reducing jitter.\n\n### Optical Transmission Basics\nOptical links use light (typically infrared lasers) to transmit data over fiber optics, offering advantages over copper: higher bandwidth, lower attenuation, and electromagnetic interference (EMI) immunity. QSFP28 modules (Quad Small Form-factor Pluggable 28) support 100 Gbps by aggregating four 25 Gbps lanes, often via Active Optical Cables (AOCs) that integrate transceivers for plug-and-play use.\n\n### Modulation and Encoding\nModulation alters a carrier signal to encode data. In digital systems like DeMoDical, techniques like PAM4 (four amplitude levels per symbol) double the data rate compared to binary NRZ (non-return-to-zero). Encoding adds redundancy (e.g., FEC) to correct errors caused by noise or dispersion in the fiber.\n\nFor further learning, refer to resources like the IEEE 802.3 standards for Ethernet optics or Xilinx/AMD documentation on UltraScale+ transceivers.\n\n## System Architecture\nThe DeMoDical architecture comprises two primary nodes connected via an optical medium:\n\n- **Transmitter Node**: \n  - Data ingestion from sources like PCIe or internal generators.\n  - Proprietary modulation and encoding in FPGA fabric.\n  - Serialization via high-speed transceivers.\n  - Optical output through QSFP28 TX lanes.\n\n- **Receiver Node**:\n  - Optical input via QSFP28 RX lanes.\n  - Deserialization and clock recovery.\n  - Proprietary decoding and error checking.\n  - Data output to host systems.\n\n![High-Speed Serial Optical Link Block Diagram](https://www.researchgate.net/publication/3244232/figure/fig8/AS:668475534086148@1536388395185/Top-level-transmitter-design-showing-clock-sources-FPGA-microwave-and-optical.png)\n\n![Transmitter and Receiver Architecture](https://www.researchgate.net/publication/224110152/figure/fig3/AS:302712513155090@1449183695998/Architecture-of-transmitter-top-and-the-receiver-bottom-inside-a-transceiver.png)\n\nUnidirectionality is enforced at the hardware level, as illustrated below:\n\n![Data Diode Installation Graphic](https://www.packetpower.com/hs-fs/hubfs/Data%20Diode%20installation%20graphic_HiRes.png?width=2877\u0026height=1875\u0026name=Data%20Diode%20installation%20graphic_HiRes.png)\n\n## Hardware Requirements\nTo replicate a DeMoDical prototype, the following components are recommended:\n\n- **FPGA Development Boards** (One for Transmitter, One for Receiver):\n  - AMD/Xilinx Kintex or Virtex UltraScale+ series with at least four 25–28 Gbps transceivers and a QSFP28 cage.\n  - Examples:\n    - BittWare XUPP3R or similar PCIe cards.\n    - Alinx AXVU series evaluation kits.\n  - Ensure Vivado compatibility for development.\n\n![XpressVUP-LP9PI FPGA Board](https://www.reflexces.com/wp-content/uploads/2024/07/XpressVUP-LP9PI-top-bot.png)\n\n![BittWare XUPP3R FPGA Board](https://www.skyblue.de/uploads/images/Produktfotos/bittware_xupp3r_xilinx_ultrascale_4x_qsfp_512_gb_sep_to_sep.jpg)\n\n- **Optical Interconnect**:\n  - 100G QSFP28 Active Optical Cable (AOC) for MMF, lengths 5–30 meters.\n  - For unidirectionality: Use breakout cables (QSFP28 to 4xSFP28) and connect only TX lanes.\n\n![Dell Compatible 100G QSFP28 AOC](https://cdn11.bigcommerce.com/s-ajtn6/images/stencil/1280x1280/products/2703/17359/QSFP28_100G_AOC_Active_Optical_Cable__32156__77763__84168.1724727927.jpg?c=2)\n\n- **Additional Accessories**:\n  - Power supplies (board-specific).\n  - Host PC with PCIe slots for data interfacing.\n\nEstimated Cost: $2,100–3,600 for a complete prototype pair (2025 pricing).\n\n## Software and FPGA Implementation\nDevelopment relies on the AMD Vivado Design Suite for FPGA configuration. The proprietary custom modulator core adapts standards like Aurora 64B/66B for point-to-point links, incorporating:\n\n- Data scrambling to prevent long runs of identical bits.\n- FEC for error resilience.\n- Lane configuration: 4 lanes at 25.78125 Gbps.\n- Validation tools: Integrated Bit Error Rate Tester (IBERT) for signal integrity.\n\nWhile HDL sources are proprietary, conceptual implementations draw from public frameworks like Corundum (an open-source 100G NIC).\n\n## Installation and Setup\n1. **Acquire Hardware**: Purchase recommended FPGA boards and AOCs from vendors like Digi-Key or FS.com.\n2. **Install Software**: Download AMD Vivado (free WebPACK edition for supported devices).\n3. **Configure FPGA**: Load proprietary bitstreams (available via licensing from DeMoD LLC).\n4. **Connect Optics**: Plug QSFP28 AOC between TX (transmitter) and RX (receiver) ports; ensure unidirectional setup by disabling RX on transmitter.\n5. **Power On and Test**: Use host software to stream test data and verify link via FPGA debug tools.\n\nDetailed setup diagrams and scripts are provided upon licensing.\n\n## Usage Guide\n- **Basic Operation**: Stream data from transmitter host to receiver; monitor via FPGA LEDs or serial console.\n- **Advanced Customization**: License holders can modify modulation parameters for specific applications (e.g., adding encryption layers).\n- **Example Scenario**: In a data diode setup, connect transmitter to a secure network output and receiver to an external analyzer.\n\n## Performance Metrics\n- **Raw Line Rate**: 100 Gbps.\n- **Effective Throughput**: 80–95 Gbps.\n- **Latency**: \u003c100 ns.\n- **BER**: \u003c10⁻¹².\n- **Power Consumption**: 15–25W per node.\n- **Distance**: Up to 100m with MMF AOCs; extendable with single-mode fiber (SMF) variants.\n\n## Troubleshooting\n- **No Link Established**: Check AOC connections, power cycles, and transceiver configurations in Vivado.\n- **High BER**: Verify fiber integrity; enable FEC and adjust equalization settings.\n- **Overheating**: Ensure adequate cooling for FPGA boards during high-throughput operation.\n- For proprietary issues, contact DeMoD LLC support.\n\n## Intellectual Property and Licensing\n© 2025 DeMoD LLC. All designs, concepts, and implementations in this repository are proprietary. Reproduction or derivative works require explicit permission. Licensing options are available for commercial use, research, or custom integrations.\n\n## Roadmap\n- Q1 2026: Release of commercial prototype kits.\n- Q2 2026: SMF extensions for longer distances (up to 10km).\n- Q3 2026: Enhanced security features, including hardware encryption modules.\n\n## Contact and Support\nFor inquiries, licensing, or technical support, please email info@demod.ltd or visit our website at demod.ltd\n\n## References and Further Reading\n- AMD/Xilinx UltraScale+ Documentation: [AMD Resources](https://www.amd.com/en/products/adaptive-socs-fpgas.html)\n- Optical Networking Standards: IEEE 802.3\n- Data Diode Concepts: NIST Guidelines on Secure Data Transfer\n- Educational FPGA Tutorials: Xilinx Vitis Tutorials on GitHub\n\nThank you for exploring the DeMoDical project. We at DeMoD LLC are committed to advancing secure communication technologies.\n\n— DeMoD LLC Team  \nDecember 23, 2025\n\n**Note**: All images are illustrative examples from public sources, depicting similar hardware and concepts. Actual DeMoDical implementations may differ.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Falh477%2Fdemodical","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Falh477%2Fdemodical","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Falh477%2Fdemodical/lists"}