{"id":35243919,"url":"https://github.com/aliceo2group/alice-fit-fpga","last_synced_at":"2026-04-10T10:02:45.406Z","repository":{"id":43273791,"uuid":"238522341","full_name":"AliceO2Group/alice-fit-fpga","owner":"AliceO2Group","description":"ALICE Fast Interaction Trigger (FIT) FPGA code","archived":false,"fork":false,"pushed_at":"2023-10-23T15:00:35.000Z","size":33733,"stargazers_count":5,"open_issues_count":1,"forks_count":5,"subscribers_count":6,"default_branch":"master","last_synced_at":"2025-09-09T03:59:22.229Z","etag":null,"topics":["alice-experiment","cern","fpga-firmware","gbt","vhdl-code","vivado"],"latest_commit_sha":null,"homepage":"","language":"VHDL","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":null,"status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/AliceO2Group.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":null,"code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null}},"created_at":"2020-02-05T18:41:35.000Z","updated_at":"2023-05-09T06:22:08.000Z","dependencies_parsed_at":"2022-09-15T15:21:42.681Z","dependency_job_id":"262456f4-0c2b-4ea7-b421-9fffc4cf49f8","html_url":"https://github.com/AliceO2Group/alice-fit-fpga","commit_stats":null,"previous_names":[],"tags_count":28,"template":false,"template_full_name":null,"purl":"pkg:github/AliceO2Group/alice-fit-fpga","repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/AliceO2Group%2Falice-fit-fpga","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/AliceO2Group%2Falice-fit-fpga/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/AliceO2Group%2Falice-fit-fpga/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/AliceO2Group%2Falice-fit-fpga/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/AliceO2Group","download_url":"https://codeload.github.com/AliceO2Group/alice-fit-fpga/tar.gz/refs/heads/master","sbom_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/AliceO2Group%2Falice-fit-fpga/sbom","scorecard":null,"host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":286080680,"owners_count":31637748,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2026-04-10T07:40:12.752Z","status":"ssl_error","status_checked_at":"2026-04-10T07:40:11.664Z","response_time":98,"last_error":"SSL_read: unexpected eof while reading","robots_txt_status":"success","robots_txt_updated_at":"2025-07-24T06:49:26.215Z","robots_txt_url":"https://github.com/robots.txt","online":false,"can_crawl_api":true,"host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["alice-experiment","cern","fpga-firmware","gbt","vhdl-code","vivado"],"created_at":"2025-12-30T05:36:52.905Z","updated_at":"2026-04-10T10:02:45.400Z","avatar_url":"https://github.com/AliceO2Group.png","language":"VHDL","funding_links":[],"categories":[],"sub_categories":[],"readme":"![PM_TCM](https://repository-images.githubusercontent.com/238522341/aca2c500-48cf-11ea-95b5-4a498a732d8e?dl=0)\n\n----\n# ALICE Fast Interaction Trigger (FIT) firmware repository\n\nAuthors: Dmitry.Serebryakov@cern.ch, Dmitry.Finogeev@cern.ch\n\n----\n## Setup\n\n### Clone the Git repository\n\n    git clone https://github.com/AliceO2Group/alice-fit-fpga.git\n\n### Update to latest version\n\n    git pull --recurse-submodules\n\n----\n### Set up Vivado 2019.2.1 (NEW !!!)\n    source /opt/Xilinx/Vivado/2019.2/settings64.sh\n\t\n\tused vivado version:\n\tVivado v2019.2.1 (64-bit)\n\tSW Build: 2729669 on Thu Dec 5 04:49:17 MST 2019\n\tIP Build: 2729494 on Thu Dec 5 07:38:25 MST 2019\n\n----\n## Generate bitstreams\n\n### FIT/FT0/PM\n\n     cd alice-fit-fpga/firmware/FT0/PM\n     vivado -mode batch -source make.tcl \n\n### FIT/FT0/TCM\n\n     cd alice-fit-fpga/firmware/FT0/TCM\n     vivado -mode batch -source make.tcl \n\n### FIT/FT0/FTM\n\n     cd alice-fit-fpga/firmware/FT0/FTM\n     vivado -mode batch -source make.tcl \n\n----\n## After any change to IP cores\n\nOpen the TCL console in the Vivado window and type in the following commands:\n\n    source ../../tcl/fit.tcl\n    fit::update_ip_properties\n\nThen git add/commit any new/changed files in the directory `ipcore_properties`\n\n----\n## After any change to IP cores and/or to VHDL source files\n\ngit add/commit any new/changed VHDL files\n\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Faliceo2group%2Falice-fit-fpga","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Faliceo2group%2Falice-fit-fpga","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Faliceo2group%2Falice-fit-fpga/lists"}