{"id":20129998,"url":"https://github.com/aliiimaher/mips-verilog","last_synced_at":"2025-08-21T22:08:45.111Z","repository":{"id":138735140,"uuid":"595273614","full_name":"aliiimaher/MIPS-Verilog","owner":"aliiimaher","description":"MIPS architecture implemented in Verilog.","archived":false,"fork":false,"pushed_at":"2023-01-30T20:05:49.000Z","size":1724,"stargazers_count":9,"open_issues_count":0,"forks_count":0,"subscribers_count":1,"default_branch":"main","last_synced_at":"2024-11-13T20:41:53.591Z","etag":null,"topics":["mips","mips-architecture","pipeline-mips","verilog"],"latest_commit_sha":null,"homepage":"","language":"C","has_issues":true,"has_wiki":null,"has_pages":null,"mirror_url":null,"source_name":null,"license":"mit","status":null,"scm":"git","pull_requests_enabled":true,"icon_url":"https://github.com/aliiimaher.png","metadata":{"files":{"readme":"README.md","changelog":null,"contributing":null,"funding":null,"license":"LICENSE","code_of_conduct":null,"threat_model":null,"audit":null,"citation":null,"codeowners":null,"security":null,"support":null,"governance":null,"roadmap":null,"authors":null,"dei":null,"publiccode":null,"codemeta":null}},"created_at":"2023-01-30T18:48:24.000Z","updated_at":"2024-03-15T04:31:52.000Z","dependencies_parsed_at":null,"dependency_job_id":"a9457cea-53a7-4052-836c-cada162c9eeb","html_url":"https://github.com/aliiimaher/MIPS-Verilog","commit_stats":null,"previous_names":[],"tags_count":0,"template":false,"template_full_name":null,"repository_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/aliiimaher%2FMIPS-Verilog","tags_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/aliiimaher%2FMIPS-Verilog/tags","releases_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/aliiimaher%2FMIPS-Verilog/releases","manifests_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories/aliiimaher%2FMIPS-Verilog/manifests","owner_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners/aliiimaher","download_url":"https://codeload.github.com/aliiimaher/MIPS-Verilog/tar.gz/refs/heads/main","host":{"name":"GitHub","url":"https://github.com","kind":"github","repositories_count":233717400,"owners_count":18718996,"icon_url":"https://github.com/github.png","version":null,"created_at":"2022-05-30T11:31:42.601Z","updated_at":"2022-07-04T15:15:14.044Z","host_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub","repositories_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repositories","repository_names_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/repository_names","owners_url":"https://repos.ecosyste.ms/api/v1/hosts/GitHub/owners"}},"keywords":["mips","mips-architecture","pipeline-mips","verilog"],"created_at":"2024-11-13T20:37:02.698Z","updated_at":"2025-01-13T08:41:14.708Z","avatar_url":"https://github.com/aliiimaher.png","language":"C","funding_links":[],"categories":[],"sub_categories":[],"readme":"# MIPS-Verilog\nMIPS architecture implemented in Verilog.\n\n-----\n\n## A 5-stage Pipelined MISP32 Processor\nFive stages of a microprocessor: \n- Instruction Fetch (IF)\n- Instruction Decode (ID)\n- Execution(EX) \n- Memory Access and Write (MEM) \n- Write Back (WB)\n![MIPS](https://user-images.githubusercontent.com/93030419/215577717-bc5c4d0b-d224-41eb-86b9-c2acf24af725.jpg)\n\n\n-----\n\n### Instructions supported:\n1. R-type Instructions (ADD, SUB, AND, OR, SLT, LSL, LSR, NOT)\n2. LW and SW\n3. ADDI\n4. BEQ\n5. SLTI\n\n-----\n\n### Supplementary Details:\n\nThis is MIPS 32 bits architecture with a 5-stage design to implement in 6 homework. And this is for the \"Computer Architecture Lab\" course at Shiraz university in Fall 2022.\n\n-----\n\n### How to run project?\n\nClone the GitHub repository and open the project folder in Xillinix to run the simulation. Note that this implementation reads the instructions from a file.\n","project_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Faliiimaher%2Fmips-verilog","html_url":"https://awesome.ecosyste.ms/projects/github.com%2Faliiimaher%2Fmips-verilog","lists_url":"https://awesome.ecosyste.ms/api/v1/projects/github.com%2Faliiimaher%2Fmips-verilog/lists"}